JP3107624B2 - Reference pattern forming method for mask alignment - Google Patents
Reference pattern forming method for mask alignmentInfo
- Publication number
- JP3107624B2 JP3107624B2 JP35401391A JP35401391A JP3107624B2 JP 3107624 B2 JP3107624 B2 JP 3107624B2 JP 35401391 A JP35401391 A JP 35401391A JP 35401391 A JP35401391 A JP 35401391A JP 3107624 B2 JP3107624 B2 JP 3107624B2
- Authority
- JP
- Japan
- Prior art keywords
- forming
- reference pattern
- cross
- pattern
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は誘電体分離ウェハの製
造方法に係り、特に素子形成用マスクを位置合わせする
ための基準パターンを形成する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a dielectric isolation wafer, and more particularly to a method of forming a reference pattern for aligning a device forming mask.
【０００２】[0002]
【従来の技術】誘電体分離ウェハは、単結晶シリコン基
板の表面に対して分離溝の形成、誘電体分離用酸化膜の
被着、支持体層としての多結晶シリコンの堆積を行った
後、前記分離溝の底部まで前記基板の裏面側を研磨して
該基板を複数の単結晶島に分離することにより製造され
る。誘電体分離集積回路装置は、前記ウェハの単結晶島
に素子を形成するが、通常前記シリコン基板の研磨側で
あるウェハの表面には基準となる位置合わせパターンが
刻まれていないため、単結晶島と素子形成用マスクパタ
ーンとを位置合わせする方法がなかった。2. Description of the Related Art A dielectric isolation wafer is formed by forming an isolation groove on a surface of a single crystal silicon substrate, depositing an oxide film for dielectric isolation, and depositing polycrystalline silicon as a support layer. It is manufactured by polishing the back surface side of the substrate to the bottom of the separation groove and separating the substrate into a plurality of single crystal islands. In the dielectric isolation integrated circuit device, elements are formed on a single crystal island of the wafer. However, since a reference positioning pattern is not engraved on the surface of the wafer which is usually a polished side of the silicon substrate, the single crystal There is no method for aligning the island with the mask pattern for element formation.
【０００３】このため、例えば単結晶島壁やグリッドラ
インを基準にして素子パターンを形成しているが、単結
晶島壁やグリッドラインは、前記シリコン基板の研磨量
のバラツキによりウェハ表面に現れる位置や幅が異なる
ため、位置合わせの基準となり得ない場合が多い。For this reason, for example, an element pattern is formed on the basis of a single crystal island wall or a grid line. However, the single crystal island wall or the grid line is located at a position appearing on the wafer surface due to a variation in the polishing amount of the silicon substrate. In many cases, they cannot be used as a reference for alignment because of differences in width and width.
【０００４】このような欠点を解決する試みとして、研
磨バラツキを考慮して複数個の形状の異なる基準パター
ンを埋め込んでおく特開昭５５−１５８６３３号公報に
記載されるような工夫もある。以下その製造方法を図６
（ａ）〜（ｃ）の工程断面図および平面図を参照して説
明する。面方位（１００）の単結晶シリコン基板に異方
性アルカリエッチング液（ＫＯＨ−イソプロピルアルコ
ール−水）を用いて分離溝を形成する際、同時に一辺の
長さがｗ1 〜ｗ4 とそれぞれ異なる正方形開口パターン
で図６（ａ）に示すように基板１に四角錐状の複数の溝
２を形成する。この時、正方形開口パターンの一辺の長
さをｗとすると、エッチング深さｄは数１で表わされる
ので、As an attempt to solve such a defect, there is a device described in Japanese Patent Application Laid-Open No. 55-158633 in which a plurality of reference patterns having different shapes are embedded in consideration of polishing variations. The manufacturing method is described below with reference to FIG.
A description will be given with reference to process cross-sectional views and plan views of (a) to (c). When a separation groove is formed on a single-crystal silicon substrate having a plane orientation of (100) using an anisotropic alkali etching solution (KOH-isopropyl alcohol-water), squares each having a different side length w 1 to w 4 at the same time As shown in FIG. 6A, a plurality of quadrangular pyramid-shaped grooves 2 are formed in the substrate 1 in an opening pattern. At this time, assuming that the length of one side of the square opening pattern is w, the etching depth d is represented by Equation 1, so that
【数１】ｗ／√２ 一辺の長さがｗ1 〜ｗ4 （ｗ1 ＞ｗ2 ＞ｗ3 ＞ｗ4 ）と
異なれば、深さｄがｄ1 〜ｄ4 （ｄ1 ＞ｄ2 ＞ｄ3 ＞ｄ
4 ）と異なって溝２が形成される。If the length of one side of w / √2 is different from w 1 to w 4 (w 1 > w 2 > w 3 > w 4 ), the depth d is d 1 to d 4 (d 1 > d 2) > D 3 > d
The groove 2 is formed differently from 4 ).
【０００５】しかる後、基板１の表面に誘電体分離用酸
化膜３を被着し、支持体層としての多結晶シリコン４を
堆積させた後、基板１の裏面側を分離溝の底部が露出す
るまで研磨するが、この時、研磨量にバラツキがあって
も、前記四角錐状の溝部においては溝２の深さがｄ1 〜
ｄ4 と異なるため、図６（ｂ）に示すようにいずれかの
基準パターン５（酸化膜３で囲まれた多結晶シリコン
４）が最適状態で単結晶シリコン基板１の研磨表面に現
れる。したがって、その最適状態の基準パターン５に図
６（ｃ）に示すように素子形成用マスクの合わせパター
ン６を位置合わせすれば、単結晶島の所定の場所に正し
く所望の素子を形成することができる。After that, a dielectric isolation oxide film 3 is deposited on the surface of the substrate 1 and polycrystalline silicon 4 is deposited as a support layer, and then the bottom of the isolation groove is exposed on the back side of the substrate 1. At this time, even if there is a variation in the polishing amount, the depth of the groove 2 is d 1 to
Since different from the d 4, (polycrystalline silicon 4 surrounded by the oxide film 3) one of the reference pattern 5 as shown in FIG. 6 (b) appears in the polishing surface of the monocrystalline silicon substrate 1 in an optimum state. Therefore, if the alignment pattern 6 of the element forming mask is aligned with the reference pattern 5 in the optimum state as shown in FIG. 6C, a desired element can be correctly formed at a predetermined position on the single crystal island. it can.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記の
ような従来の基準パターン形成法では、複数の基準パタ
ーンを形成しなければならないので、基準パターン形成
用に広いスペースを必要とする問題点があった。また、
溝の深さを異ならせるために深い溝を形成しなければな
らないので、この時同時に形成される単結晶島形成用分
離溝の形状を崩すことがあった。さらに複数の基準パタ
ーンが出現するため、どのパターンにマスクを合わせて
良いのか迷い、素子形成の作業性を悪くすることがあっ
た。However, in the conventional method for forming a reference pattern as described above, a plurality of reference patterns must be formed, so that a large space is required for forming the reference pattern. Was. Also,
Since a deep groove must be formed in order to vary the depth of the groove, the shape of the single crystal island forming separation groove formed at the same time may be broken. Further, since a plurality of reference patterns appear, it is sometimes unclear which pattern should be matched with the mask, and the workability of element formation may be degraded.
【０００７】この発明は上記の点に鑑みなされたもの
で、上記従来の欠点を解決し得る基準パターンの形成法
を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a method of forming a reference pattern which can solve the above-mentioned conventional disadvantages.
【０００８】[0008]
【課題を解決するための手段】この発明では、誘電体分
離ウェハの製造方法において、分離溝の形成時、同時
に、十字状の開口部を有するマスクを用いて基準パター
ン用の溝を基板に形成し、その後、誘電体分離用絶縁膜
および支持体層の形成を行った後研磨を行うことによ
り、前記絶縁膜で囲まれた支持体材料からなる十字星状
の基準パターンを研磨表面に露出させる。According to the present invention, in a method of manufacturing a dielectric isolation wafer, a groove for a reference pattern is formed on a substrate at the same time as forming an isolation groove by using a mask having a cross-shaped opening. Then, after forming an insulating film for dielectric isolation and a support layer, polishing is performed to expose a cross star-shaped reference pattern made of a support material surrounded by the insulating film to the polished surface. .
【０００９】[0009]
【作用】上記この発明においては、十字星状の基準パタ
ーンが得られ、この基準パターンは研磨量のバラツキに
より図５（ａ），（ｂ）に示すように拡大、縮小はする
が、４つの先端は常に十字パターンの中心線ｌx ，ｌy
上に位置する。したがって、この十字星状パターンの４
つの先端に素子形成用マスクの十字パターン１９を合わ
せれば、研磨量のバラツキに関係なく常に素子形成用マ
スクを正確に位置合わせすることができる。According to the present invention, a cross-shaped reference pattern is obtained. The reference pattern is enlarged and reduced as shown in FIGS. 5A and 5B due to the variation in the polishing amount. The tip is always the center line lx, ly of the cross pattern
Located on top. Therefore, the cross star pattern 4
If the cross pattern 19 of the element forming mask is aligned with one of the tips, the element forming mask can always be accurately positioned regardless of the variation in the polishing amount.
【００１０】[0010]
【実施例】以下この発明の一実施例を図１〜図４を参照
して説明する。図１および図２において、（ａ）は平面
図、（ｂ）は断面図である。図３は断面図、図４は研磨
側（基板裏面側）から見た平面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. 1 and 2, (a) is a plan view and (b) is a cross-sectional view. FIG. 3 is a cross-sectional view, and FIG. 4 is a plan view seen from the polishing side (substrate back side).
【００１１】図１において、１１は面方位（１００）の
単結晶シリコン基板、１２はその表面に形成されたエッ
チングマスク材としての酸化膜、１３はその酸化膜１２
にホトリソ・エッチング技術により形成された十字状の
開口部である。前記シリコン基板１１の表面に前記酸化
膜１２を形成し、これに後に形成される単結晶島を分離
するための開口部を形成して、その開口部からアルカリ
異方性エッチング液（ＫＯＨ−イソプロピルアルコール
−水）でシリコン基板１１の表面に単結晶島型形成用分
離溝を形成する。この酸化膜１２に単結晶島を分離する
ための開口部を形成する際、酸化膜１２に前記十字状の
開口部１３を形成する。また、前記アルカリ異方性エッ
チング液でシリコン基板１１の表面に単結晶島型形成用
分離溝を形成する際、酸化膜１２に形成された開口部１
３から基板１１表面に図２に示すように基準パターン用
の溝１４を形成する。この溝１４は、全体の平面形状が
十字状で、その４つの先端から中心に向かってＶ型の溝
が次第に深くなるように、さらに内部のコーナー部１５
は（１１１）面よりエッチング速度が速い（ｎｎ１）面
が現れる結果、他より深くなるように形成される。In FIG. 1, reference numeral 11 denotes a single-crystal silicon substrate having a plane orientation of (100), 12 denotes an oxide film formed on the surface thereof as an etching mask material, and 13 denotes an oxide film
A cross-shaped opening formed by the photolithographic etching technique. The oxide film 12 is formed on the surface of the silicon substrate 11, an opening for separating a single crystal island to be formed later is formed, and an alkali anisotropic etching solution (KOH-isopropyl) is formed through the opening. An isolation groove for forming a single crystal island is formed on the surface of the silicon substrate 11 by using alcohol-water. When forming an opening for separating a single crystal island in the oxide film 12, the cross-shaped opening 13 is formed in the oxide film 12. Further, when forming the single crystal island type forming separation groove on the surface of the silicon substrate 11 with the alkali anisotropic etching solution, the opening 1 formed in the oxide film 12 is formed.
From 3, a groove 14 for a reference pattern is formed on the surface of the substrate 11 as shown in FIG. 2. The groove 14 has an overall corner shape 15 such that the overall planar shape is a cross shape, and the V-shaped groove gradually becomes deeper from the four ends toward the center.
Is formed so as to be deeper than others as a result of the appearance of the (nn1) plane having an etching rate higher than that of the (111) plane.
【００１２】しかる後、エッチングマスクとしての酸化
膜１２を除去した後、分離溝および溝１４部分を含む基
板１１の全表面に図３に示すように誘電体分離用の酸化
膜１６を形成し、さらにその上に支持体層としての多結
晶シリコン１７を堆積させる。Thereafter, after removing the oxide film 12 as an etching mask, an oxide film 16 for dielectric isolation is formed on the entire surface of the substrate 11 including the isolation groove and the groove 14 as shown in FIG. Further, polycrystalline silicon 17 as a support layer is deposited thereon.
【００１３】しかる後、基板１１の裏面側を分離溝の底
部が露出するまで研磨して該基板１１を複数の単結晶島
に分離するが、この時前記溝１４部分においては前記の
ような溝であることにより、酸化膜１６で囲まれた多結
晶シリコン１７からなる十字星状の基準パターン１８が
図４に示すように研磨表面に露出する。この十字星状の
基準パターン１８は、前記基板の研磨量が例えば図３の
ｐ1 ，ｐ2 というようにバラツクと、図５（ａ），
（ｂ）に示すように拡大，縮小はするが、４つの先端は
常に十字パターンの中心線ｌx ，ｌy 上に位置する。し
たがって、この十字星状基準パターン１８の４つの先端
に素子が形成用マスクの十字パターン１９を図５に示す
ように合わせれば、研磨量のバラツキに関係なく常に素
子形成用マスクを正確に位置合わせすることができる。Thereafter, the back surface of the substrate 11 is polished until the bottom of the separation groove is exposed to separate the substrate 11 into a plurality of single crystal islands. As a result, the cross-shaped reference pattern 18 made of polycrystalline silicon 17 surrounded by the oxide film 16 is exposed on the polished surface as shown in FIG. The cross star-shaped reference pattern 18 has a variation in the polishing amount of the substrate, for example, p 1 and p 2 in FIG.
As shown in FIG. 3B, the four ends are always positioned on the center lines lx and ly of the cross pattern. Therefore, when the elements are aligned with the four ends of the cross star-shaped reference pattern 18 with the cross pattern 19 of the mask for forming the element as shown in FIG. 5, the element forming mask is always accurately positioned regardless of the variation in the polishing amount. can do.
【００１４】[0014]
【発明の効果】以上詳細に説明したようにこの発明によ
れば、十字星状の基準パターンにより研磨量のバラツキ
に関係なく常に素子形成用マスクを正確に位置合わせす
ることができる。そしてこの発明によれば基準パターン
を１つとすることができるので、基準パターンのための
スペースを少なくすることができるとともに、マスク合
わせ時に迷うことがなく作業性の向上を図ることができ
る。さらに基準パターン用の溝も特に深くする必要がな
いので、同時に形成される単結晶島形成用分離溝の形状
を崩すこともなくなる。As described above in detail, according to the present invention, the element forming mask can always be accurately positioned by the cross star-shaped reference pattern regardless of the variation in the polishing amount. According to the present invention, since one reference pattern can be used, the space for the reference pattern can be reduced, and the workability can be improved without being lost at the time of mask alignment. Further, since it is not necessary to particularly deepen the groove for the reference pattern, the shape of the single crystal island forming separation groove formed at the same time is not broken.
【図１】この発明の一実施例の一部を示す平面図および
断面図である。FIG. 1 is a plan view and a sectional view showing a part of an embodiment of the present invention.
【図２】この発明の一実施例の一部を示す平面図および
断面図である。FIG. 2 is a plan view and a sectional view showing a part of one embodiment of the present invention.
【図３】この発明の一実施例の一部を示す断面図であ
る。FIG. 3 is a sectional view showing a part of one embodiment of the present invention.
【図４】この発明の一実施例の一部を示す平面図であ
る。FIG. 4 is a plan view showing a part of one embodiment of the present invention.
【図５】この発明の一実施例における基準パターンの露
出状態を示す平面図である。FIG. 5 is a plan view showing an exposed state of a reference pattern in one embodiment of the present invention.
【図６】従来の基準パターン形成法を示す断面図および
平面図である。FIG. 6 is a cross-sectional view and a plan view showing a conventional reference pattern forming method.
１１ 単結晶シリコン基板 １４ 溝 １６ 酸化膜 １７ 多結晶シリコン １８ 基準パターン DESCRIPTION OF SYMBOLS 11 Single crystal silicon substrate 14 Groove 16 Oxide film 17 Polycrystalline silicon 18 Reference pattern
Claims (1)
第１の面と平行な第２の面を有する半導体基板におい
て、 前記第１の面上に、第１の絶縁膜を形成する工程と、 前記第１の絶縁膜に、所定の幅の十字状パターンの開口
部を形成し、前記第１の面を露出する工程と、 露出した前記第１の面を、ＫＯＨ―イソプロピルアルコ
ール―水よりなる異方性エッチングで所定量エッチング
する工程と、 前記第１の絶縁膜を除去した後、前記第１の面上に第２
の絶縁膜を形成する工程と、 前記第２の絶縁膜上に多結晶シリコン膜を形成する工程
と、 前記半導体基板の前記第２の面を研磨することにより、
前記所定の幅より小さい幅の十字状パターンに前記多結
晶シリコン膜を露出させることを特徴とするマスク位置
合わせのための基準パターン形成方法。1. A semiconductor substrate having a first surface having a plane orientation of (100) and a second surface parallel to the first surface, wherein a first insulating film is formed on the first surface. Forming an opening of a cross-shaped pattern having a predetermined width in the first insulating film, exposing the first surface; and removing the exposed first surface with KOH-isopropyl. Etching a predetermined amount by anisotropic etching composed of alcohol-water, and removing the first insulating film, and then forming a second layer on the first surface.
Forming a polycrystalline silicon film on the second insulating film, and polishing the second surface of the semiconductor substrate.
A method of forming a reference pattern for mask alignment, comprising exposing the polycrystalline silicon film to a cross-shaped pattern having a width smaller than the predetermined width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35401391A JP3107624B2 (en) | 1991-12-19 | 1991-12-19 | Reference pattern forming method for mask alignment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35401391A JP3107624B2 (en) | 1991-12-19 | 1991-12-19 | Reference pattern forming method for mask alignment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05166772A JPH05166772A (en) | 1993-07-02 |
| JP3107624B2 true JP3107624B2 (en) | 2000-11-13 |
Family
ID=18434726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35401391A Expired - Fee Related JP3107624B2 (en) | 1991-12-19 | 1991-12-19 | Reference pattern forming method for mask alignment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3107624B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4531713B2 (en) * | 2006-03-31 | 2010-08-25 | 三菱電機株式会社 | Alignment mark and method for forming the same, semiconductor device and method for manufacturing the same |
-
1991
- 1991-12-19 JP JP35401391A patent/JP3107624B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05166772A (en) | 1993-07-02 |
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