JPS60167439A - Manufacture of complementary dielectric isolation substrate - Google Patents
Manufacture of complementary dielectric isolation substrateInfo
- Publication number
- JPS60167439A JPS60167439A JP2343784A JP2343784A JPS60167439A JP S60167439 A JPS60167439 A JP S60167439A JP 2343784 A JP2343784 A JP 2343784A JP 2343784 A JP2343784 A JP 2343784A JP S60167439 A JPS60167439 A JP S60167439A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- single crystal
- polishing
- grown
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
イ、産業上の利用分野
不発明は、一枚の半導体基板上に、絶縁膜により互いに
分離された、n型とp型の素子形成用の単結晶島を有す
る相補型絶縁分離基板の製造方法に関する。Detailed Description of the Invention A. Industrial Application Field The invention is a complementary semiconductor substrate having single crystal islands for forming n-type and p-type elements separated from each other by an insulating film on one semiconductor substrate. The present invention relates to a method for manufacturing a type insulating isolation substrate.
口、従米技術
相補型誘電体分離基板は、p型シリコン基板を用いても
n型シリコン基板を用いても製造可能であり、不発明も
どちらの導電型のシリコン基板を用いた場合でも適用す
ることができるが。Complementary technology dielectric isolation substrates can be manufactured using either p-type silicon substrates or n-type silicon substrates, and the invention also applies regardless of whether silicon substrates of either conductivity type are used. Although you can.
ここではn型シリコン基板を用いた場合1r:説明する
。n形シリコン基板を用いた相補型誘電体分離基板は、
n型シリコン基板を異方性エツチングすることにより形
成したn島と、異方性工、チング後にp型シリコンをエ
ピタキシャル成長させて形成したp島とを有する。p型
シリコンをエピタキシャル成長させた後にシリコン基板
のエピタキシャル成長した面を研磨する必要があるが、
この研磨は、n島上につくられたチニックパターン全目
安に行っている。n島上のシリコン酸化膜の一部分を開
孔して単結晶を露出すせておき、p島をエピタキシャル
成長ニよって形成する際に、開孔部に成長する単結晶全
チェックパターンとして利用している。チェックパター
ンは開孔幅によって決まるため、開孔幅を変えて、高さ
の異なるチェックパターンをつくっておき、どの扁さの
チェックパターン筐で見えるか全研磨の目安にしている
。n島上からの距離の小さい、すなわち、画さの低いチ
ェックパターンは、シリコン酸化膜の開孔幅も狭く、そ
の部分に成長したシリコンの幅も細いため、研磨が、そ
のチェックパターンに達していても、単結晶シリコンと
多結晶シリコンの区別がしにくいこともあって、そのチ
ェックパターンが現われていても確認できずに研磨を過
剰に行って、n島上のシリコン酸化膜が露出する危険が
ある。研磨によってシリコン酸化膜が無用すると、後の
様々なエツチング工程によって。Here, a case 1r using an n-type silicon substrate will be explained. A complementary dielectric isolation substrate using an n-type silicon substrate is
It has an n-island formed by anisotropically etching an n-type silicon substrate, and a p-island formed by epitaxially growing p-type silicon after the anisotropic etching. After epitaxially growing p-type silicon, it is necessary to polish the epitaxially grown surface of the silicon substrate.
This polishing is performed on all the tinic patterns formed on the n-island. A portion of the silicon oxide film on the n-island is opened to expose the single crystal, and when the p-island is formed by epitaxial growth, it is used as a check pattern for all the single crystals that will grow in the opening. Since the check pattern is determined by the width of the aperture, we create check patterns of different heights by changing the aperture width, and use this as a guideline for all polishing to determine which width of the check pattern casing will be visible. A check pattern with a small distance from the n-island, that is, a low definition, has a narrow opening in the silicon oxide film and a narrow width of the silicon grown in that area, so polishing has not reached the check pattern. However, it is difficult to distinguish between single-crystal silicon and polycrystalline silicon, so even if the check pattern appears, it cannot be confirmed and there is a risk of excessive polishing and exposing the silicon oxide film on the n-island. . Once the silicon oxide film is rendered useless by polishing, it is removed by various later etching steps.
その膜厚が薄くなり、p島にP+層を形成する際にシリ
コン酸化膜がマスクとして役に立たず。The film thickness becomes thinner, and the silicon oxide film becomes useless as a mask when forming the P+ layer on the p-island.
n島にアクセプタ不純物が導入されてしまう可能性が高
く、このようなn島に、後に素子を形成しても満足な特
性は得られない。このため、過剰な研磨によってn島上
の酸化rMが露出することは避けなければならない。There is a high possibility that acceptor impurities will be introduced into the n-island, and even if an element is later formed on such an n-island, satisfactory characteristics will not be obtained. Therefore, it is necessary to avoid exposing the oxidized rM on the n-island due to excessive polishing.
ハ1発明の目的
不発明は、上記のn島上からの距離の小さいチェックパ
ターンは8i認しにくいという欠点を可能とした製造方
l!I!i:を提供することを目的としている。C1 Purpose of the invention The non-invention is a manufacturing method that makes it possible to overcome the drawback that it is difficult to recognize the check pattern at a small distance from the n-island as described above! I! The purpose is to provide i:.
二0発明の構成
不発明によれば、−4電型シリコン卑結晶基板に対し異
方性エツチングを行い、つぎに絶縁分離用の酸化膜全形
成し、写真食刻技術により前記絶縁酸化膜の一部分は広
い開孔部分を作っておき、つぎに反対導電型のシリコン
を薄くエピタキシャル成長させ、さらに酸化全行い、こ
の酸化により形成された酸化(換のうち前記開孔部分に
成長した単結晶シリコン上の酸化膜のみを残し、つぎに
厚くシリコンをエピタキシャル成長させた後、前記広い
開孔部分に成長したシリコン単結晶を研磨チェックパタ
ーンとして前記厚くエピタキシャル成長させたシリコン
面ヲ研磨することを含む相補型誘電体分離基板の製造方
法が得られる。According to the present invention, anisotropic etching is performed on a base silicon substrate of a -4 voltage type, and then an oxide film for insulation isolation is entirely formed, and the insulation oxide film is removed by photolithography. A wide opening is made in one part, and then a thin layer of silicon of the opposite conductivity type is grown epitaxially, followed by complete oxidation. A complementary dielectric comprising: leaving only an oxide film of the silicon, then epitaxially growing a thick layer of silicon, and then polishing the silicon surface grown thickly and epitaxially using the silicon single crystal grown in the wide opening as a polishing check pattern. A method for manufacturing a separated substrate is obtained.
ホ、実施例 つぎに不発明を実施例によ!ll説明する。E, Example Next, let's take a look at examples of non-invention! I will explain.
第1図ta+ないしtelは不発明の一実施例全説明す
るための製造工程順の仕掛品基板の断面図である。第1
図(alは、n型シリコン基板11に対し異方性エッチ
ングケした後に酸化を行い、つぎに写真食刻技術により
酸化膜のうちの不要部分を除去して有用部分の酸化膜2
を残した状態を示している。この時、n型単結晶島1a
の部分のシリコン酸化膜には大きい開孔幅の開孔1bが
あけられている。つぎに同図(blのように、p型シリ
コンヲ博<エピタキシャル成長させる。FIGS. 1A to 1D are cross-sectional views of a work-in-progress board in the order of the manufacturing process to fully explain an embodiment of the present invention. 1st
Figure (al) shows that the n-type silicon substrate 11 is anisotropically etched and then oxidized, and then unnecessary parts of the oxide film are removed by photolithography and the oxide film 2 of the useful parts is removed.
It shows the state where . At this time, n-type single crystal island 1a
An aperture 1b having a large aperture width is formed in the silicon oxide film at a portion indicated by . Next, as shown in the same figure (bl), p-type silicon is grown epitaxially.
5−
その結果、p型巣結晶シリコン層3.多結晶シリコン層
4.結晶欠陥を多数含むp型車結晶シリコンからなる遷
移領域5が形成される。つぎに酸化し、写真食刻技術に
より、同図(C)に示すように、シリコン酸化膜の開孔
部分1bK成長したp形単結晶シリコン上にのみシリコ
ン酸化膜6を残して他の部分は除去する。っき゛に、p
形シリコンを厚くエピタキシャル成長させる。5- As a result, p-type nested crystalline silicon layer 3. Polycrystalline silicon layer 4. A transition region 5 made of p-type crystalline silicon containing many crystal defects is formed. Next, the silicon oxide film 6 is left only on the p-type single crystal silicon grown on the open hole part 1bK of the silicon oxide film, and the other parts are removed by oxidation and photolithography, as shown in FIG. Remove. clearly, p
Grow thick silicon epitaxially.
その結果、同図fdlに示すように、p型巣結晶シリコ
ン層3、多結晶シリコン層4%遷移領域5はその筐ま成
長すると共に、酸化膜6の上には多結晶シリコン7が成
長する・次に研磨全行う−が、研磨が進んでシリコン酸
化膜の開孔部1bに成長した単結晶部分に研磨が達する
と、広い単結晶部分が現われて、これ以上研磨全続行す
るとn島1のシリコン酸化膜が露出する危険があること
を警告する。したがって、この時点で研磨を中止する。As a result, as shown in fdl in the same figure, the p-type nested crystalline silicon layer 3 and the polycrystalline silicon layer 4% transition region 5 grow to their casings, and the polycrystalline silicon 7 grows on the oxide film 6.・Next, complete polishing is performed - but as the polishing progresses and reaches the single crystal part that has grown in the opening 1b of the silicon oxide film, a wide single crystal part appears, and if the polishing continues any further, n-island 1 Warning that there is a risk of exposing the silicon oxide film. Therefore, polishing is stopped at this point.
この状態が第1図fatである。This state is fat in FIG.
へ1発明の効果
上述のとおり、本発明方法では、シリコン酸 6−
化膜の開孔1bの幅を十分大きくしておけば、その部分
に成長した単結晶が研磨によって現われたことが容易に
確認できる。これを従来のチェックパターンと併用する
ならば、過剰な研磨を未然に防止でき、n島のシリコン
酸化膜が研磨によって露出する危険もなくなシ、良好な
単結晶島を有する相補型誘電体分離基板を得ることがで
きる。1. Effects of the Invention As mentioned above, in the method of the present invention, if the width of the opening 1b in the silicon oxide film is made sufficiently large, it is easy to see that the single crystal that has grown in that part appears by polishing. You can check it. If this is used in conjunction with a conventional check pattern, excessive polishing can be prevented, there is no risk of the silicon oxide film on the n-islands being exposed by polishing, and complementary dielectric isolation with good single-crystal islands can be achieved. A substrate can be obtained.
第1図fatないしtelは不発明の一実施例全説明す
るための製造工程順の仕掛品基板の断面図である。
11・・・・・n型単結晶シリコン基板、1.la・・
・・・・n型シリコン単結晶島、ib・・・・・酸化膜
の広い開孔部、2 ・・・・絶縁分離用酸化膜、3・・
・・・p型シリコン単結晶層、4・・・・・・多結晶シ
リコン層、5・・・・・・遷移領域、6・・・・・・開
孔部単結晶体シリコン上の酸化膜、7 ・・・・開孔部
多結晶シリコン層。
7−FIGS. 1 through 1 are cross-sectional views of a work-in-progress board in the order of manufacturing steps to fully explain an embodiment of the present invention. 11...N-type single crystal silicon substrate, 1. la...
...N-type silicon single crystal island, ib...Wide opening in oxide film, 2...Oxide film for insulation isolation, 3...
... p-type silicon single crystal layer, 4 ... polycrystalline silicon layer, 5 ... transition region, 6 ... oxide film on opening single crystal silicon , 7...Opening polycrystalline silicon layer. 7-
Claims (1)
行い、つぎに絶縁分離用の絶縁膜を形成し、写真食刻技
術により前記絶縁酸化膜の一部分に広い開孔部分を作っ
ておき、つぎに反対導電型のシリコン會薄くエピタキシ
ャル成長させ、さらに酸化を行い、この酸化により形成
された酸化膜のうち前記開孔部分に成長した単結晶シリ
コン上の酸化膜のみを残し、つぎに厚くシリコンをエピ
タキシャル成長させた後、前記広い開孔部分に成長した
シリコン単結晶全研磨チェックパターンとして前記厚く
エピタキシャル成長させたシリコン面全研磨することを
含む相補型誘電体分離基板の製造方法。Anisotropic etching is performed on a silicon single crystal substrate of one conductivity type, an insulating film for insulation isolation is formed, a wide opening is made in a part of the insulating oxide film by photolithography, and then A thin film of silicon of the opposite conductivity type is grown epitaxially, and then oxidized. Of the oxide film formed by this oxidation, only the oxide film on the single crystal silicon grown in the opening is left, and then a thick silicon layer is grown epitaxially. and then completely polishing the silicon surface grown epitaxially to a large extent as a check pattern for polishing the entire silicon single crystal grown in the wide opening portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2343784A JPS60167439A (en) | 1984-02-10 | 1984-02-10 | Manufacture of complementary dielectric isolation substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2343784A JPS60167439A (en) | 1984-02-10 | 1984-02-10 | Manufacture of complementary dielectric isolation substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60167439A true JPS60167439A (en) | 1985-08-30 |
Family
ID=12110475
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2343784A Pending JPS60167439A (en) | 1984-02-10 | 1984-02-10 | Manufacture of complementary dielectric isolation substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60167439A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5243200A (en) * | 1990-11-22 | 1993-09-07 | Canon Kabushiki Kaisha | Semiconductor device having a substrate recess forming semiconductor regions |
US6500694B1 (en) | 2000-03-22 | 2002-12-31 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US7041178B2 (en) | 2000-02-16 | 2006-05-09 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US10366962B2 (en) | 1999-10-01 | 2019-07-30 | Invensas Bonding Technologies, Inc. | Three dimensional device integration method and integrated device |
US11760059B2 (en) | 2003-05-19 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Method of room temperature covalent bonding |
-
1984
- 1984-02-10 JP JP2343784A patent/JPS60167439A/en active Pending
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5243200A (en) * | 1990-11-22 | 1993-09-07 | Canon Kabushiki Kaisha | Semiconductor device having a substrate recess forming semiconductor regions |
US5602057A (en) * | 1990-11-22 | 1997-02-11 | Canon Kabushiki Kaisha | Process of making a semiconductor device using crystal growth by a nucleation site in a recessed substrate and planarization |
US10366962B2 (en) | 1999-10-01 | 2019-07-30 | Invensas Bonding Technologies, Inc. | Three dimensional device integration method and integrated device |
US9331149B2 (en) | 2000-02-16 | 2016-05-03 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US7041178B2 (en) | 2000-02-16 | 2006-05-09 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US7335572B2 (en) | 2000-02-16 | 2008-02-26 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US8053329B2 (en) | 2000-02-16 | 2011-11-08 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US9082627B2 (en) | 2000-02-16 | 2015-07-14 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US9391143B2 (en) | 2000-02-16 | 2016-07-12 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US10312217B2 (en) | 2000-02-16 | 2019-06-04 | Invensas Bonding Technologies, Inc. | Method for low temperature bonding and bonded structure |
US7037755B2 (en) | 2000-03-22 | 2006-05-02 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6627531B2 (en) | 2000-03-22 | 2003-09-30 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6500694B1 (en) | 2000-03-22 | 2002-12-31 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US11760059B2 (en) | 2003-05-19 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Method of room temperature covalent bonding |
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