JPS6022733Y2 - Receiver for vehicle control equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiver for receiving railway signals such as train speed indication signals, such as an on-board receiver for an automatic train control system.

FIG. 1 shows an example of this type of conventional receiver. This receiver receives an amplitude-modulated signal corresponding to a railway signal such as a train speed instruction signal, which is transmitted to a ground track circuit by an on-board antenna (not shown). (This signal has a frequency that differs depending on the indicated speed) is inputted to the bandpass filter 1 from the input terminal IN to remove the noise component, and the signal after the noise removal is envelope detected by the envelope line detector 2. After extracting low frequencies (approximately 10 Hz to 100 Hz) with the low-pass filter 3 and shaping the waveform, the signal wave selection circuits 41 to 4n individually select the target signals fm, and output them via the lower priority circuit 5 to output 0UT1. ~0UTn.

Note that the signal wave selection circuits 41 to 4° include a limiter 6,
It consists of a selection amplifier 7, a level detector 8, a time setting circuit 9, an amplifier 10, and a rectifier circuit 11.

However, in this conventional receiver, the signal wave selection circuit 4
Since the frequency of the signal fm input to 1 to 4n is set to be as low as about 10 to 100 Hz in order to improve the S/N ratio, the capacitors etc. for frequency selection become large, making it difficult to downsize. The drawback is that it cannot meet demands.

In order to eliminate this drawback, as shown in FIG.
m is the signal wave selection circuits 131 to 13n (the circuits include the selection amplifier 7, the level detector 8, the amplifier 10, and the rectifier 1).
It is conceivable to perform frequency selection by inputting the signal into a frequency filter (consisting of 1).

As the multiplier circuit 12 shown in FIG. 2, the one shown in FIG. 3 has already been proposed.

This circuit generates a control signal T having a lower frequency than the signal fm by a timing generation circuit 14, as shown in FIG.
, T and clock pulse CP for writing and reading
, generate nCP and write (when T=゛1')
, a shift pulse sp is sent to the shift register 17 via the AND circuit 15 and the OR circuit 16, and the signal fm is stored in the shift register via the AND circuit 18 and the OR circuit 19. ), the high-frequency clock pulse nCP is sent as a shift pulse SP to the shift register 17 via the AND circuit 20 and the OR circuit 16, and the output is sent to the AND circuit 21 and the OR circuit 1.
The output signal nfm is re-inputted into the shift register 17 via 9, and the frequency is multiplied by the AND circuit 22.
This is what you get.

Note that T in Figure 4.

is one period of register reading.

However, in this circuit, frequency selection cannot be performed while T=66199, and the period of this control signal T is equal to the signal f
In addition, as shown in Figure 4, there are variations in the time from the time the signal changes until the output is output, so there is a large variation in the response time of the receiver. There is.

In order to compensate for this drawback, as shown in FIG. 5, a system in which two circuits of the circuit shown in FIG. 3 are provided has been devised.

That is, shift registers 17a, 17b similar to the shift register 17 in FIG. 3, output analogues 22a, 22
b. Input and shift pulse gate circuit 23 a.
23b, an output OR circuit 24 is provided, and as shown in FIG. 6, the output nf is always output from the AND circuit 22a or 22b.
Make sure that m is obtained.

With this configuration, the output can be taken out in a temporally continuous manner, and it is also possible to reduce variations in the time from signal change to output output.

However, even in this circuit, time variations still remain, and although the output is continuous, the two registers 1
7a and 17b, the phase often becomes discontinuous at the time of switching.

In the example of Fig. 6, the signal fm is 1 m2 from fml at the time when it is
As a result, a waveform in which two waves such as nfx are superimposed on the output signal nfrn appears, and the phase becomes discontinuous, and at the time tl, an output corresponding to f.

The purpose of this invention is to minimize the variation in time from the time of signal input until obtaining a signal whose frequency has been multiplied as much as possible, and to prevent the occurrence of discontinuous parts in the output signal when switching signals. An object of the present invention is to provide a receiver for a vehicle control device having such a configuration.

In order to achieve this objective, the receiver for a vehicle control device of the present invention has a first clock running at a frequency sufficiently higher than the frequency of the signal obtained by shaping the received railway signal.
a second counter that increments with a clock having a frequency that is an integral multiple of the frequency of the clock, and a memory that is addressed by the outputs of these counters, each time the first counter increments. The shaped signal waveform is sub-ringed and stored at the address of the memory specified by the output of the first counter, and each time the second counter increments, the signal waveform specified by the output of the second counter is stored. The present invention is characterized in that the content of the address of the memory is read out, and the read output is frequency-selected.

The details of the present invention will be explained below with reference to the drawings.

FIG. 7 shows an embodiment of the present invention, and only the portion corresponding to the multiplier circuit 12 in FIG. 2 is shown.

30 is a first counter that increments with a clock CP having a frequency sufficiently higher than the signal fm after shaping the railway signal such as the train speed instruction signal, and 31 is a clock nCP having a frequency that is an integral number (n) times that of the clock. In this embodiment, the output signal of the second counter 31 is passed through the data 32 to create a clock CP which is an integer n/n of the clock nCP, and this is incremented by the first counter. An example with 30 inputs is shown.

33 is a random access memory (RAM) as a memory for storing signal waveforms; 34 is a RAM by selecting each output of the first counter 30 and the second counter 31;
33 as an address signal, and the data selector is configured such that when the output CP of the decoder 32 is on,
That is, each time the first counter 30 increments, the output of the tenth counter 30 is selected, and in other cases, the output of the second counter 31 is selected.

The output of the decoder 32 is also applied to the RAM 33, and R
This becomes the AM write command signal.

35 is a buffer circuit that stores the output of the RAM 33 at each read timing.

Next, we will explain an example of the operation of this circuit using RA for easy understanding.
A model in which M33 is 32 bits will be explained with reference to the time chart of FIG.

FIG. 8 shows the case where n=4, and the output of the first counter 30 is stored in the RAM 3 every time the clock CP is added and incremented.
3 as an address signal, and a write command is added to the RAM 33, and writing of all bits is completed in the time Tyu, and the write operation is repeated from the next clock CP.

On the other hand, the data written in the RAM 33 is read out at four times the writing speed using the output of the second counter 31 as the address of the RAM 33.

T. indicates one cycle of reading.

In FIG. 8, three examples 1.2.3 are given as the output nfm.

The output nfm of each side 1 to 3 is different, but this is due to the relationship between the first counter 30 and the second counter 31 at the time of signal change.

In other words, even if the value of the first counter 30 at the time of signal change, which is the start time of this time chart, is defined as 0,
Without loss of generality, the value of the second counter 31 at this point takes any value of 0, 2.4, . .3 shows the output waveform when the values of the second counter 31 at the start of the signal change are 21 and 16XO, respectively.

FIG. 9 is an example of a circuit that is a more specific version of the circuit shown in FIG. 36c to 36c are used as the second counter 31, and 36c to 36e are used as the first counter 30.

37a to 37c are 4-bit data selectors, and each data selector 37a, 37b, 37c corresponds to the counters 36a and 36c, 36b and 36d, 36c and 36e, respectively.
When the overflow signal 38 (that is, clock CP) of the counter 36b is "1°", the selectors 37at, 37bt, and 37c are switched to the counters 36C, 36d, and 36e, respectively. Select the output of
When the signal 38 is 0, the counter 36 a?
Select the output of 36 by 36 c.

The RAM 33 has a configuration of 4096 x 1 bits, the above-mentioned shaped signal fm is added to the data input end, and the above-mentioned overflow signal 38 is connected to the write command terminal W via a two-canand circuit 40 with the clock nCP via an inversion circuit 39.
, so that writing is possible only when the signal 38 is "1".

Further, the inverting circuit 41 and the NAND circuit 42 create a signal that causes the buffer flip-flop 35 to be inactive during writing and to be activated during reading.

In the circuit of Figure 9, if the frequency of nCP is IMHz, the frequency of CP is 1 of 25, that is, 3, gK
Hz, and while cp is 4091, the counter 36a~
The output of 36c is selected by data selectors 37a to 37C and given as an address of RAM 33, and a read operation is performed.

On the other hand, when CP becomes "1", data selectors 37a to
37c selects the outputs of counters 36c to 36e and uses them as address signals.

Therefore, a write operation is performed at a speed of 17256 times that of a read operation.

Note that the frequency of the signal fm stored in the RAM 33 is 16
Hz~77Hz, nfm is 4.1KHz~19.
It is 7KdL.

FIG. 10 shows a change in the multiplier frequency component appearing in the output when the input signal changes in the circuit shown in FIG.

a shows the level change of multiplier signals njA and nfB when the signal changes from fA to fB, and the signal level of nfA gradually decreases from the time of signal change until the end of writing all bits, and the signal level of nfB gradually decreases. Levels increase gradually.

Therefore, by setting the trigger level in the subsequent sorting circuit that sorts out signals with multiple diameters to a level L that is between the maximum value (max) of each signal or a level slightly lower than that, fA and fB of the sorting circuit can be set. The corresponding outputs become as shown in A and B, respectively, and there is no discontinuity like the circuit shown in Figure 5, and the corresponding selection outputs can be obtained after a certain period of time from the point of signal change. Recognize.

Further, even if there is a momentary interruption of the signal as shown in b, or if noise corresponding to fA occurs when there is no signal as shown in c, no change occurs in the output after selection.

Therefore, the signal wave selection circuits 131 to 13 of FIG. It is not necessary to provide the time setting circuit 9 required in the signal wave selection circuits 41 to 4n of FIG. 1.

In addition, when two waves are received at the same time as shown in d, it includes each frequency, the difference between the two waves, the sum, and its harmonic components, and when two waves are superimposed, each signal The output level will be lower than when there is only one wave, but if the receiving operation level L of each signal is set lower than the level when two waves are superimposed, both waves can be detected as shown in the figure. I can do it.

Note that although the receiver in Fig. 2 shows an example in which signal wave selection circuits 13□ to 13n are provided for each signal, the signal wave selection covers the frequency range of the input signal or its multiples. It is also possible to adopt other configurations, such as a configuration in which a variable frequency circuit is provided to compare the frequency with an input signal, and when the frequencies match, output a signal that displays the signal.

As described above, the receiver of the present invention includes a memory and an eleventh second counter that is incremented by a low-speed clock and a high-speed clock, and the first counter is incremented each time the first clock increments. The shaped signal waveform is sampled and stored at the specified memory address, and each time the second counter increments, the content of the memory address specified by the second counter is read out. Since the output is frequency-selected, the frequency input to the signal wave selection circuit becomes higher, and the signal wave selection circuit becomes smaller. Needless to say, the device becomes more compact. There is no variation in time from point to point to output point, and output can be obtained in a short time at discontinuous portions.

Furthermore, according to the present invention, since the change in the frequency component that appears in the output after the signal changes is proportional to time, by appropriately setting the operating level of the signal wave selection circuit,
Since the operating time and recovery time as a receiver can be stably obtained, a time setting circuit is not required, which also contributes to miniaturization of the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional receiver, FIG. 2 is a block diagram showing an example of the configuration of another receiver, FIG. 3 is a circuit diagram showing a frequency multiplier circuit that has already been proposed, and FIG. Figure 4 is a time chart explaining its operation, Figure 5 is a circuit diagram showing a frequency multiplier circuit that compensates for the shortcomings of the circuit in Figure 3, Figure 6 is a time chart explaining its operation, and Figure 7. 8 is a block diagram showing an example of the frequency multiplier circuit that is the main part of the present invention, FIG. 8 is a time chart explaining its operation, FIG. 9 is a circuit diagram showing a specific example of FIG. 7, and FIG. 3 is a time chart showing an example of the operation of the receiver of the present invention. 30...First counter, 31...Second counter, 33...Memory, 34...
··decoder.

Claims (1)

[Scope of utility model registration request] A first counter that increments with a clock whose frequency is sufficiently higher than the frequency of the signal obtained by shaping the received railway signal, and a second counter which increments with a clock whose frequency is an integral multiple of the frequency of the clock. counters and a memory addressed by the outputs of these counters, and each time the first counter increments, the shaped signal is sampled at the address of the memory designated by the output of the first counter. and storing the contents of the address in the memory specified by the output of the second counter every time the second counter increments, and frequency-selecting the read output. A receiver for a vehicle control device characterized by: