SU1420612A1 - Data extraction device - Google Patents

Abstract

The invention relates to the technique of magn. records The purpose of the invention is to increase the reliability of data extraction. The device comprises a phase locked loop 5, a frequency divider 6, a decoder 7, a bus 8 of reproduced signals and a bus 9 of selected data. The introduction of delay line 1, multiplexer 2, D-flip-flop 3, reversible counter 4, and the formation of new connections between device elements allows, in a steady state, to track the position of the data in the time window and automatically keep the input data in the center of the time window, which reduces the likelihood The accuracy of errors during data extraction. 2 Il.

Description

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The invention relates to a magnetic recording technique, in particular, to devices for extracting data from a reproduced signal of a storage device with a movable magnetic carrier.

The purpose of the invention is to increase the reliability of data extraction.

FIG. i shows the block diagram of the proposed device; in fig. 2 - timing diagrams, the letter designations of which correspond to the same points of the diagram.

The device contains a multi-tap I delay line, a multiplexer 2, a D-flip-flop 3, a reversible counter 4, a phase locked loop 5, a frequency divider 6, a decoder 7, a bus 8 of reproduced signals, and ujHHy 9 selected data.

The device works as follows.

The first impulse of the reproduced signal from H1INA 8 through the multi-drop delay line and multiplexer 2 is fed to the synchronization input of the D-flip-flop, to the second input of which the frequency is supplied to the second input of the auto-tuning frequency twice the frequency. On the rising edge, D-trigger 3 records the position of the data in a time window, centered on the rising edge of the double frequency signal from the output of phase locked loop 5. If the D-trigger is set to the zero state, it means that the impulse data is not in the center of the window, but is shifted. Reversible counter 4 increases its value by one and according to the new address multiplexer 2 selects the next large data delay from multi-drop 1 delay line. The next reproduced signal again analyzes the position of the data in the time window. If the D-flip-flop 3 remains in the zero position again, the reversible counter 4 increases its value by one and select

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The following large data delay occurs from multi-drop 1 delay line. The data delay increases until the data pulse edge passes the center of the time window. In this case, D-Trig5 ger 3 is set to one and the device begins the process of reducing the delay time, i.e. the reversible counter 4 starts counting on the subtraction, and the delay of the signals arriving from

10 of the multiple-tap delay line 1, through multiplexer 2 to D-flip-flop 3, is reduced. In the steady state mode, continuous tracking of the position of the data in the time window allows automatic retention of the input data in the center of the time window

5 which reduces the likelihood of errors during data extraction.

Invention invention

A data extractor comprising a decoder whose output is connected to the dedicated data bus, a frequency divider, a reproduced signal bus and a phase locked loop, the output of which is connected to the decoder’s first input through a frequency divider, in order to increase the reliability of the selection data, it is equipped with a multi-echo, reversible counter, a D-flip-flop and a multi-tap delay line connected to the bus of the reproduced signals,

0 and tapping to the information inputs of the multiplexer, the address inputs of which are connected to the outputs of the reversible counter, and the output connected to the synchronization input of the D-flip-flop, to the counting input of the reversible counter and the second input of the decoder, while the middle tap of the multi-hop delay line is connected to the input of the phase locked loop, the output of which is connected to the D input of the D-flip-flop, and the output of the latter is connected to the control input of the reversible counter.

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Claims (1)

Claim A data extraction device comprising a decoder, the output of which is connected to the extracted data bus, a frequency divider, a reproduced signal bus and a phase locked loop, the output of which is connected through the frequency divider to the first input of the decoder, characterized in that, in order to increase the reliability of data extraction, it is equipped with a multiplexer, a reversible counter, a D-trigger and a multi-tap delay line connected by an input to the bus of reproduced signals, and taps to the information inputs of the multiplexer, whose address inputs are connected to the outputs of the reverse counter, and the output is connected to the synchronization input of the D-trigger, to the counting input of the reverse counter and to the second input of the decoder, while the middle tap of the multi-tap delay line is connected to the input of the phase locked loop, the output of which is connected to D -the input of the D-flip-flop, and the output of the latter is connected to the control input of the reverse counter. d Fig g