JPS60226151A - Hybrid integrated circuit with terminal pattern subject to wider connecting space - Google Patents
Hybrid integrated circuit with terminal pattern subject to wider connecting spaceInfo
- Publication number
- JPS60226151A JPS60226151A JP59081715A JP8171584A JPS60226151A JP S60226151 A JPS60226151 A JP S60226151A JP 59081715 A JP59081715 A JP 59081715A JP 8171584 A JP8171584 A JP 8171584A JP S60226151 A JPS60226151 A JP S60226151A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- terminal
- scribe line
- terminal pattern
- space
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3405—Edge mounted components, e.g. terminals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は基板の表裏面にパターンを形成した混成ＩＣに
係り、特に、端子の接続する端子部パターンの接続面積
を広く形成するに好適な広い接続面積の端子部パターン
を有する混成ＩＣに関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a hybrid IC in which patterns are formed on the front and back surfaces of a substrate. The present invention relates to a hybrid IC having a terminal pattern with a large connection area.
各電子機器には基板の表裏面にパターンを形成する混成
ＩＣが採用されている。一般に混成ＩＣは１個毎に製作
されずに大形の基板を分割切断し多数個数シするのが特
長とされる。混成ＩＣの端子部パターンには端子が接続
されるが、多数個＠、シされた各混成ＩＣの表裏面の端
子部パターンにずれがあると、所望の接続面積が確保さ
れず、歩留を低下すると共に、信頼性を低下させる欠点
が生じる。Each electronic device employs a hybrid IC in which patterns are formed on the front and back surfaces of a substrate. In general, a hybrid IC is characterized in that it is not manufactured one by one, but rather is cut into pieces from a large substrate to produce a large number of pieces. Terminals are connected to the terminal pattern of the hybrid IC, but if there is a misalignment between the terminal patterns on the front and back surfaces of each hybrid IC, the desired connection area will not be secured and the yield will be reduced. As this decreases, a drawback arises that reduces reliability.
すなわち、第１図および第２図に示す如く、混成ＩＣを
製作するには基板１０表裏面に同一形状のパターンを同
一位置に形成する。すなわち、表面には第１図に示す如
く表面端子部パターン３が、裏面には裏面端子部パター
ン４がそれぞれ形成される。次に表面端子部パターン３
の位置に合わせて分割切断のためのスクライプ線２を形
成し、これに沿って基板１を切断する。That is, as shown in FIGS. 1 and 2, in order to manufacture a hybrid IC, patterns of the same shape are formed at the same position on the front and back surfaces of the substrate 10. That is, as shown in FIG. 1, a front terminal pattern 3 is formed on the front surface, and a back terminal pattern 4 is formed on the back surface. Next, surface terminal pattern 3
A scribe line 2 for dividing and cutting is formed in accordance with the position of , and the substrate 1 is cut along this line.
この際、表面端子部パターン３と裏面端子部パターン４
とが全く同一位置および同一形状に形成されれば問題な
いが、第２図に示す如く、裏面端子部パターン４とスク
ライブ線２とが交差する場合が生じる。これは、印刷、
ホト９ングツフイ等によるパターン形成時の表裏の位置
ずれや、レーザ、回転ブレードによるダイシング等によ
る合わせずれによるものである。At this time, the front terminal pattern 3 and the back terminal pattern 4
There is no problem if they are formed in exactly the same position and shape, but as shown in FIG. 2, there are cases where the back terminal pattern 4 and the scribe line 2 intersect. This is printed,
This is due to misalignment between the front and back sides during pattern formation using photonography or the like, or misalignment due to dicing using a laser or rotating blade.
第３図（Ａ）はスクライブ線２に対し裏面端子部パター
ン４が上側にずれ７”Ｃ場合を示し、この混成ＩＣに端
子７を接続させると、その表面側は表面端子部パターン
３とほぼ同一面積の接続面積の表面端子部導体５が得ら
れるが裏面側には上記のずれ分だけ小さい接触面積の裏
面端子部導体６が得られることになシ、全体としてずれ
分だけ端子７との接触面積が減少する。第６図（Ｂ）は
スクライブ線２に対し裏面端子部パターン４が下側にず
れた場合を示し、この場合にも上記と同様にずれ分だけ
端子７との接触面積を減少させる。この減少度合が大き
い場合には製品不良となり歩留シを低下せしめると共に
、品質の安定性を欠き、信頼性を低下させる原因となる
。FIG. 3(A) shows a case where the back side terminal pattern 4 is shifted upward by 7"C with respect to the scribe line 2. When the terminal 7 is connected to this hybrid IC, the front side is almost the same as the front side terminal pattern 3. Although a front terminal conductor 5 with the same connection area is obtained, a back terminal conductor 6 with a contact area smaller by the above deviation is obtained on the back side, and overall the contact area with the terminal 7 is reduced by the deviation. The contact area decreases. FIG. 6(B) shows a case where the back terminal pattern 4 is shifted downward with respect to the scribe line 2, and in this case as well, the contact area with the terminal 7 is reduced by the amount of shift as described above. If the degree of this decrease is large, the product will be defective and the yield will be lowered, and this will cause a lack of quality stability and lower reliability.
本発明は、以上の欠点を解決すべく創案されものであ）
、その目的は表裏面のパターンずれが生じても所望の接
触面積を確保し、歩留および信頼性を向上せしめる広い
接触面積の端子部パターンを有する混成ＩＣを提供する
ことにある。The present invention was created to solve the above drawbacks.)
The purpose is to provide a hybrid IC having a terminal pattern with a wide contact area, which ensures a desired contact area even if pattern deviation occurs between the front and back surfaces, and improves yield and reliability.
本発明は、上記目的を達成するために、基板の表裏面の
いづれか１つの面の端子部パターンと合致する池の面の
端子部パターンの面積を、少なくとも上記表裏面に形成
されるパターンの相対ずれ量分だけ上記１つの面の端子
部パターンの面積よシも大キくシ、上記表裏面の端子部
パターンに係合する端子との接触面積を所望値に形成す
るようにした広い接触面積の端子部パターンを有する混
成ＩＣを特徴とし友ものである。In order to achieve the above-mentioned object, the present invention reduces the area of the terminal pattern on the surface that matches the terminal pattern on any one of the front and back surfaces of the substrate to at least the area of the pattern formed on the front and back surfaces. The area of the terminal part pattern on the one surface is larger by the amount of deviation, and the contact area with the terminal that engages with the terminal part pattern on the front and back surfaces is formed to a desired value. It features a hybrid IC with a terminal pattern.
以Ｔ１本発明の実施例を図面ｉ′ｃ基づき説明する。 Hereinafter, an embodiment of the present invention will be described based on drawing i'c.
まず、本実施例の概要を説明する。First, an overview of this embodiment will be explained.
第４図に示す如く、例えば裏面の端子部パターン４ａに
対応する下ずれスクライブ線９および上ずれスクライブ
線１０と標準スクライブ線８との相対ずれ量を一Δおよ
び十ｌとする。As shown in FIG. 4, for example, the relative deviations between the standard scribe line 8 and the downwardly displaced scribe line 9 and upwardly displaced scribe line 10 corresponding to the terminal pattern 4a on the back surface are 1 Δ and 10 l.
裏面の端子部パターン４ａの面積を上記の相対ずれ量ｌ
の２倍だけ大きくすると、端子７と混成ＩＣとは表面の
端子部パターン３とほぼ同一の所望の接続面積が得られ
ることになる。The area of the terminal pattern 4a on the back side is determined by the above relative shift amount l.
If the terminal 7 and the hybrid IC are made twice as large as , the terminal 7 and the hybrid IC will have a desired connection area that is almost the same as that of the terminal pattern 3 on the front surface.
次に、本実施例を詳細に説明する。すなわち、上記した
如く、表裏面のパターンの標準スクライブ線８を基準と
する上記相対ずれ量ｌはパターンの位置すれとスクライ
ブ線の位置ずれ等によシ定められ、ばらつきのある値と
なるが、鮭験又は統計的手法等によシ推定することが可
ＩＩ。Next, this embodiment will be explained in detail. That is, as described above, the above-mentioned relative deviation amount l of the pattern on the front and back sides with respect to the standard scribe line 8 is determined by the positional deviation of the pattern and the positional deviation of the scribe line, etc., and has a variable value. It can be estimated using salmon experiments or statistical methods.
でろ・る。上記した如く、標準スクライプＩｖＪ８は表
面のパターンを基準にして形成されるので、裏面の端子
部パターン４ａＫ対応する下ずれスクライプ繍９卦よｒ
に１−−Ｐれスクライブ線１ｎけμ記の推定された相当
ずれ量Δだけずれることになる。Dero-ru. As mentioned above, since the standard scripe IvJ8 is formed based on the pattern on the front side, the downwardly shifted scripe embroidery 9 corresponding to the terminal pattern 4aK on the back side
1--P, the scribe line 1n is shifted by an estimated equivalent shift amount Δ.
そこで、裏面の端子部パターン４ａの面積を上記の相当
ずれ量ｌの２倍だけ表面の端子部パターン３よシも大き
く形成する。Therefore, the area of the terminal pattern 4a on the back surface is made larger than that of the terminal pattern 3 on the front surface by twice the above-mentioned equivalent deviation amount l.
第５図（Ａ）は８面の端子部パターン４ａが標準スクラ
イブ線８の上側にずれ次場合で、標準スクライブ線８と
下ずれスクライブ線９とも一致せしめて端子７を係合す
ると、裏面端子部導体６ａと端子７とは表面端子部導体
５と同一面積だけ接触し、所望の接触面積を確保するこ
とができる。また第５図（Ｂ）は裏面の端子部パターン
４ａが標、準スクライプ線８の下側にずれたもので、標
準スクライブ線８と上ずれスクライブ線１０とを一致せ
しめて端子７を係合することにより上記と同様に所望の
接触面積が確保され□る。FIG. 5(A) shows a case in which the terminal pattern 4a on the eight sides is shifted above the standard scribe line 8, and when the standard scribe line 8 and the downwardly shifted scribe line 9 are aligned and the terminal 7 is engaged, the back side terminal The portion conductor 6a and the terminal 7 are in contact with the surface terminal portion conductor 5 over the same area, so that a desired contact area can be secured. In addition, in FIG. 5(B), the terminal pattern 4a on the back side is shifted to the lower side of the standard, semi-scribe line 8, and the terminal 7 is engaged by aligning the standard scribe line 8 and the upwardly shifted scribe line 10. By doing so, the desired contact area can be secured in the same manner as above.
以上により表裏パターンのパターンずれやスクライブ線
の位置ずれに基づくずれが生じても、真が１ルな償１１
摺餅１イ瓜ム剖ス這虐Ｔρ小Ａヱ７との接触面積を少な
くとも所望値にすることが可能となるため歩留シが向上
し、かつ製品品質の安定化が図れ信頼性が向上する。As a result of the above, even if a deviation occurs due to a pattern deviation between the front and back patterns or a positional deviation of a scribe line, the true value is 11.
Since it is possible to make the contact area with Surimochi 1 to at least the desired value, yield is improved, product quality is stabilized, and reliability is improved. do.
本実施例において裏面の端子部パターン４ａを大きな面
積としたが、逆に表面の端子部パターンを大きクシ、裏
面のスクライブ線を基準とするようにしても勿論かまわ
ない。In this embodiment, the terminal pattern 4a on the back surface has a large area, but it is of course possible to use a large comb as the terminal pattern on the front surface and use the scribe line on the back surface as a reference.
Ｃ発明の効果〕
以上の説明によって明らかの如く、本発明によれば表裏
のパターンずれに関係なく、端子との所望接触面構を確
保し、歩留ルおよび信頼性を向上し得る効果が上げられ
る。C. Effects of the Invention] As is clear from the above explanation, the present invention has the effect of ensuring the desired contact surface structure with the terminal regardless of pattern misalignment on the front and back sides, and improving yield and reliability. It will be done.
第１図は基板の表面に形成される端子部パターンとスク
ライブ線との位置関係を示す模式図、第２図は基板の裏
面に形成される端子部パターンとスクライブ線との位置
関係を示す模式図、第３図（Ａ）、（Ｂ）は従来の表裏
端子部パターンと端子との接触状態を示す模式図、第４
図は本発明一実施例の端子部パターンとスクライブ線と
の位置関係を示す模式図、第５図（Ａ）、（Ｂ目家実施
例の表裏端子パターンと端子との接触状態を示す模式図
である。
１・・・基板、２・・・スクライブ線、３・・・表面端
子部パターン、４，４ａ・・・裏面端子部パターン、５
・・・表面端子部導体、６．６ａ・・・裏面端子部導体
、７・・・端子、８・・・標準スクライブ線、９・・・
上ずれスクライブ線、１０・・・上ずれスクライブ線。
代理人弁理士 高 橋 明 夫
□□□□□−−−
第 ３ 聞
（Ａ）
（８）Figure 1 is a schematic diagram showing the positional relationship between the terminal pattern formed on the front surface of the board and the scribe line, and Figure 2 is a schematic diagram showing the positional relationship between the terminal pattern and scribe line formed on the back side of the board. Figures 3(A) and 3(B) are schematic diagrams showing the contact state between the conventional front and back terminal patterns and the terminals.
The figures are a schematic diagram showing the positional relationship between the terminal pattern and the scribe line in one embodiment of the present invention, FIG. 1... Board, 2... Scribe line, 3... Surface terminal pattern, 4, 4a... Back terminal pattern, 5
...Surface terminal part conductor, 6.6a...Back surface terminal part conductor, 7...Terminal, 8...Standard scribe wire, 9...
Upward deviation scribe line, 10... Upward deviation scribe line. Representative Patent Attorney Akio Takahashi □□□□□--- Third hearing (A) (8)
Claims (1)
成する混成ＩＣにおいて、上記表裏面のいずれか１つの
面の端子部パターンと合致ン する池の面の端子部パターンの面積を、少なｄも、上記
表裏面に形成されるパターンの相対すれ量分だけ上記１
つの面の端子部パターンの面積よｐも大きく形成したこ
とを特徴とする広い接続面積の端子部パターンを有する
混成■Ｃ０[Scope of Claims] In a hybrid IC in which a pattern to which a terminal is connected is formed on the terminal portions on the front and back surfaces of a substrate, a terminal portion on a side surface that matches the terminal portion pattern on any one of the front and back surfaces. The area of the pattern is reduced by the amount of relative displacement between the patterns formed on the front and back surfaces.
A hybrid with a terminal pattern with a wide connection area, which is characterized by the area p being larger than the area of the terminal pattern on one surface ■C0
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59081715A JPS60226151A (en) | 1984-04-25 | 1984-04-25 | Hybrid integrated circuit with terminal pattern subject to wider connecting space |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59081715A JPS60226151A (en) | 1984-04-25 | 1984-04-25 | Hybrid integrated circuit with terminal pattern subject to wider connecting space |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60226151A true JPS60226151A (en) | 1985-11-11 |
Family
ID=13754093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59081715A Pending JPS60226151A (en) | 1984-04-25 | 1984-04-25 | Hybrid integrated circuit with terminal pattern subject to wider connecting space |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60226151A (en) |
-
1984
- 1984-04-25 JP JP59081715A patent/JPS60226151A/en active Pending
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