JPS60225460A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the improvement in decrease of transistor-driving power accompanying voltage drops by a method wherein a low developing cost and a short developing period for alteration of the wall structure are sufficient by providing electrode contacts for setting wall region reference potentials and electrode contacts for setting substrate reference potentials. CONSTITUTION:Both the transistor group in a well 12 constituting a CMOS transistor group and the transistor group formed on the side of a substrate 11 forming a pair therewith are provided with the contacts 16 and 19 of electrode 17 and 18 for setting reference potentials. Therefore, in alteration of the type of wells, the reduction of developing cost and developing period can be contrived because it becomes unnecessary to alter the patterns of the contact 16 and 19 and said electrodes 17 and 18 continuous thereto. Besides, each transistor group of transistors TP formed on the side of the substrate 11 is provided with the contact 19 for setting substrate reference potentials; accordingly, the local voltage drops in the substrate 11 caused by substrate resistance can be prevented, and the decrease of transistor-driving power can be improved.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a complementary integrated circuit, etc., in which a large number of P-channel field effect transistors and paired N-channel field effect transistors are formed on the same substrate. The present invention relates to a type of semiconductor device.

[Technical background of the invention]

The structure of a complementary MO8 (hereinafter abbreviated as CMO8) in a conventional integrated circuit is as shown in FIG. 1 and FIG. 2, which schematically shows the structure taken along line AA' in FIG.

That is, for example, a plurality of p
A well 12 is formed, and each P well 12 has a plurality of N channel transistors TN arranged in a row. As is well known, in this N-channel transistor TN, a pair of N-type diffusion layers 13w, which are spaced apart from each other and serve as source and drain regions, are formed on a substrate 11, and are sandwiched between the pair of diffusion layers 13 through a dirt oxide film 14. The structure has a structure in which a dirt electrode I5 is formed on the area where the dirt is formed.

Furthermore, on one side of the P-well 12 of the semiconductor substrate 1, a P-type diffusion layer 13F forming a pair with each of the N-channel transistors TN formed in each P-well 12 is provided.
A P-channel FET is formed.

A pair of these P-channel transistors T and N-channel transistors TH is connected to a dirt electrode 15.
becomes common.

Note that in FIG. 2, a part of the dart electrode 15 is omitted.

Furthermore, since each well 12 is formed independently, each well 12 is provided with at least one P-type contact portion 16 for potential setting so that the potential of each well 12 does not float.
is provided, and the well 12 is connected via this contact portion 16.
A well region reference potential setting electrode 17 (not shown in FIG. 2) is connected to the well region reference potential setting electrode 17 (not shown in FIG. 2). Also, on the substrate 11 side, one substrate reference potential setting electrode 18 is provided for a plurality of groups of CMO transistors 8).

[Problems in the Background Art] By the way, there are often cases where it is desired to commercialize an integrated circuit, etc., developed and manufactured with a P-well structure as a second source, etc. with an N-well structure.In this case, for example, the device shown in FIG. When the conductivity types of the substrate 11 and the well 12 are reversed, the area within the broken line 10 in FIGS. 1 and 2 becomes a well.

However, if this continues, the potential of the well will float, so it is necessary to newly design a contact portion for applying a reference potential to each well and a wiring layer notn following the contact portion. Therefore, even if the well conductivity type is simply reversed, it is necessary to redesign the wiring, etc., and the development time and development costs associated with commercialization are required.

Also, a plurality of groups of P-channel transistors T on the substrate 11 side
On the , side, a problem has arisen in that the driving force of the transistor T formed in the remote part from the contact part 19 of the substrate reference potential setting electrode 18 decreases due to the voltage drop due to the substrate resistance of the substrate 11.

[Purpose of the invention]

The present invention has been developed in view of the above points, and it reduces the development cost and development period when changing the well structure of a semiconductor device, and reduces the need for driving transistors due to the voltage drop caused by the substrate resistance of a busy semiconductor substrate. An object of the present invention is to provide a semiconductor device with improved power drop.

[Summary of the invention]

That is, the semiconductor device according to the present invention includes a semiconductor substrate of one conductivity type, a well region of the other type formed in this semiconductor substrate, and at least one conductivity type formed in this well region.
one type of field effect transistor, an electrode contact portion for setting a well region reference potential provided in the well region, and one type of field effect transistor of the well region so as to form a pair with the one type field effect transistor page. It is provided with at least one electrode contact part for setting a field effect base potential of the other type formed on the side and an electrode contact part for setting a substrate reference potential provided to form a pair.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In the plan view of FIG. 3, each well I of the semiconductor substrate 11
2 is provided with a contact portion 16 for setting a reference potential. In each well 12, some N
Channel transistors TN are formed, and a pair of N-channel transistors TN and a dirt electrode 15 are formed on one side of the well 12 at positions corresponding to these transistors TN.
form a common P-channel transistor T.

Here, a substrate 11 on which a group of P-channel transistors T is formed has a transistor T in the well 12 in a region adjacent to the group of P-channel transistors T.
An N-type contact portion 19 for setting a reference potential of the substrate is formed in a positional relationship between the reference potential setting electrode 17 and the reference potential setting electrode 17, and a reference electrode is inserted into the contact portion 19 and connected to the substrate. A potential setting electrode 18 is provided.

In this way, the well 1 constituting the transistor group (0MO8)
In the case where reference potential setting electrodes 17.18 (7) and contact portions 16.19 are provided on both the transistor group in 2 and the paired transistor group formed on the substrate 11 side, When changing the contact part 16.
Since there is no need to change the reference potential setting electrodes 17 and 18 that are busy therewith, the development cost and development period can be reduced.

In addition, in such a device, since a contact portion 19 for setting a substrate reference potential is provided for each group of transistors T formed on the substrate 11 side, a local potential drop in the substrate 11 due to substrate resistance can be prevented. This can be prevented and the reduction in driving power of the transistor can be improved.

Note that the contact portion 1619 of the reference potential setting electrode is the third
Not only are they formed in symmetrical positions with respect to the arrangement of transistors forming the CMOS transistor group as shown in the figure, but the arrangement of the transistor group and the arrangement of the contact portions 16° 19 are point symmetrical as shown in Fig. 4. It may be formed in such a position. Further, the contact portions 16, 19 are not necessarily provided in a ratio of one pair to one group of 0MO8) transistors, but may be provided in plural pairs.

〔Effect of the invention〕

As described above, according to the present invention, the development cost and development period when changing the well structure of a semiconductor device can be reduced.
It is possible to provide a semiconductor device in which a reduction in driving power of a transistor due to a voltage drop due to substrate resistance of a semiconductor substrate is improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a conventional semiconductor device, FIG. 2 is a cross-sectional view schematically showing a cross section taken along line AA' in FIG. 1, and FIG. 3 is a plan view of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a plan view showing another embodiment of the present invention. 1... Semiconductor substrate, 12... Well, 13Nm1
3F...diffusion layer, 14...f-) oxide film, 15...
- Dirt electrode, 16... Well region reference potential setting electrode, 17.18... Contact portion, 19... Substrate reference potential setting electrode. Applicant's agent Patent attorney Takehiko Suzue 1st j:I Figure 2

Claims (1)

[Scope of Claims] A semiconductor substrate of one conductivity type, a well region of the other type formed in this semiconductor substrate, at least one field effect transistor of one side formed in the well region, an electrode contact portion for setting a well region reference potential provided in the well region; and at least one electric field of the other type formed on one side of the well region so as to form a pair with the field effect transistor of the one type. an electrode contact part for setting a substrate reference potential, which is provided on the substrate at a location adjacent to the other type of field effect transistor so as to form a pair with the electrode contact part for setting the well region reference potential; A semiconductor device comprising: