JPS60225194A - Display control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a display control circuit that controls a display device equipped with a display RAM.

[Technical Background of the Invention] Conventionally, when display data is stored in a RAM (Random Access Memory), a display signal is formed based on the data read from the RAM, and a liquid crystal display is driven with this display signal, This is performed using a display control circuit as shown in FIG.

In FIG. 1, 1 is an arithmetic processing circuit, for example, CPtJ. This CPLll includes common signals C0M1 to COMj of jm, a frame signal FR1 having a period corresponding to the period of these three common signals, and a row address signal x 1 used when a storage circuit described later is used for normal data storage. to Xj and column address signals Y1 to Y
m, data Dco or Di to be stored in the storage circuit;
Read/write control signals R, 'W, chip selection signal C8,
Then, an O-lock signal φ is generated. 2 is a liquid crystal display. This liquid crystal display 2 is supplied with j common signals 001VI1 to COMj, t-3 generated by the CPU 1 and a segment signal R1 that is generated by a display interface circuit described later. The display is driven by a signal. Reference numeral 3 denotes a memory circuit that stores data, and is made up of memory cells arranged in 11 directions and column directions. 4 is a row decoder that selects memory cells in the memory circuit 3 in the row direction, and 5 is a column decoder that selects memory cells in the memory circuit 3 in the column direction. Reference numeral 6 denotes a data control circuit for writing and reading data to and from one memory cell in the memory circuit 3 selected by the column decoder 5. 7 is an n-ary counter which counts the clock signal φ from the CPU 1 and supplies the count output to the row decoder 4 as one of the row address signals Z1 to Zj. 8 consists of an AND gate, an OR gate, J: and an inverter, and according to the chip selection signal QC8, the row address signals X1 to XJ from the CPU 1 and the 11 address signals z1 to ZJ from the n-ary counter 7 are processed. This is a selection circuit that selectively outputs either one to the row decoder 4.

A timing signal generating circuit 9 is supplied with the frame signal FR1 and the clock signal φ, and generates a clear signal CL for the upper advance counter 7 and a frame synchronization signal FR2 for the display interface circuit from these signals. Reference numeral 10 denotes a display interface that forms segment signals to be supplied to the liquid crystal display 2 based on one row of data read out from the storage circuit 3 and the frame synchronization signal FR2 from the timing signal generation circuit 9. It is a circuit.

The timing signal generation circuit 9 is composed of two clocked inverters and an impark, and includes a half-pitch shift 1~ type synchronization circuit 21 for synchronizing the frame signal FR1 with the clock signal φ, and also two clocked inverters. JjJ, and an inverter, and the above synchronous circuit 2
The synchronous circuit 2 is composed of a shift inverter and an inverter, and shifts the output signal a of the clock signal φ by a half pitch i of the clock signal φ.
A synchronous circuit 23 of the type Shift 1 to make the output signal of Shift 2 half the bit of the clock signal φ.
The synchronous circuit 23 is composed of an AND gate 24 to which the output signal C from the clocked inverter in the preceding stage of the synchronous circuit 22 and the output signal a of the synchronous circuit 21 are supplied.
The output signal of
The output signal of 24 is respectively supplied to the n-ary counter 7 as a clear signal CL.

In such a configuration, when the memory circuit 3 is used for normal data storage, the 1-tub selection signal CS is set to normal, and the row address (No. 8 x 1 to Xj, column address Signals Y1 to Ym are output.By setting the chip selection signal CS to the level, the selection circuit 8 selects the row address signals x1 to Xj from the CPU.Therefore, at this time, the memory circuit 3 The address is designated based on the row address signals R X 1 to Xj and the column address signals Y1 to Ym, and the
Fixing or reading data D1 to Dl11
be called.

FIG. 2 is a timing chart showing each signal when displaying the liquid crystal display 2. At this time, the CPU 1 sends j common signals COM1 to COMj, frame signals FRI and The clock signal φ is sequentially supplied.The AND gate 24 in the timing signal generation circuit 9 generates a clock signal (: 0) at the rise of the frame signal FR1, and a clear signal having a pulse width of 1 bit of the clock signal φ. CL is output.And every time this clear signal CL is input, the n-ary counter 7 is reset.After being reset, the n-ary counter 7 inputs the clock signal φ], and its count output z1 or Zj (second
In the figure, j-3 (ie, the n-ary counter 7 is an octal counter) is incremented as shown.

On the other hand, at this time, the device block selection signal C8 constituted by the CPU 1 is set to O level, and the row address signals Z1 to z3 from the selection 0+Jn3i counter 7 are selected. Therefore, by the output of the row counter 4 based on the output signal from the n-ary counter 7, the memory circuits in the 0th to 7th rows of the memory circuit 3 are sequentially addressed.
The data of each row is sequentially input to the display interface circuit 10 in parallel. Here, the data Din input to the display interface circuit 10 in parallel is from the same row as the count of the n-ary counter 7 as shown in FIG. Further, the timing signal generation circuit 9 optically generates a frame synchronization signal FR2 synchronized with the common signal C0M1 from the frame signal FR1. Based on the frame synchronization signal FR2 and the data Din of 811, the display interface circuit 10 delays the latched data for one row by one clock of the clock signal φ and outputs it to the display segment of the liquid crystal display 2. A segment signal SEG whose voltage level is set so that an alternating current voltage is always supplied is generated and is supplied to the liquid crystal display 2. Therefore, as shown in FIG. 2, this segment signal SEG is synchronized with each common signal COMI to CON•1j. The liquid crystal display 2 is driven for display by each common signal C0M1 to COMj and the corresponding segment signal SEG.

[Problems in the Background Art] By the way, when displaying on the liquid crystal display 2 in the above-mentioned conventional circuit, the row decoder 4 is supplied with row address signals z1 to Zj from the n-ary counter 7 and outputs the row address signals J5. The counter 7 is cleared by a clear signal CL generated by the timing signal generation circuit 9. As shown in FIG. 2, this clear signal CL is a frame signal FR1.
Since it is generated only at the rising edge of , when displaying, it is necessary to set the number of bits of the n-ary counter 7 so as to obtain the number 1-value corresponding to the number of rows of data to be stored in the memory circuit 3. . For example, when the number of rows of data to be stored in the storage circuit 3 is eight as described above, the number of bits of the n-ary counter 7 must be set to three. However, conventionally, the number of bits of the decimal counter 7 is fixed. η, when displaying line number data different from the above, the n-ary counter 7 must be newly configured (1), resulting in a lack of versatility.

[Object of the Invention] The present invention has been made in consideration of the above circumstances, and its purpose is to provide a highly versatile display control circuit that can display various line number data. It is in.

[Summary of the Invention] In order to achieve the above object, the present invention includes a liquid crystal display that is driven for display by a plurality of common signals and a signal to segment 1, and a ceramic panel with a number of rows corresponding to the number of common signals. 1- A memory circuit for storing data, a counter for counting clock signals and specifying a row address of the memory circuit according to the count output, and a segment read from the row of the memory circuit addressed by this counter. A display interface circuit that forms the segment signal based on the data and a frame signal having a period corresponding to the period of the plurality of common signals are supplied, and are synchronized with the clock signal at the rise and fall of the frame signal, respectively. and a timing signal generation circuit that generates a clear signal for the counter, and the counter is cleared every cycle of the common signal.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a circuit diagram of one embodiment of the display control circuit according to the present invention, showing only the timing signal generation circuit. Note that the other configurations are the same as those shown in FIG. 1 above.

In this embodiment circuit, there is one rming signal optical generation circuit 19.
The timing shown in FIG.
AND gate 2 to which the output signal C from the clocked inverter in the previous stage of 2 and the output signal @a of the synchronous circuit 21 are supplied.
4, and further includes the above-mentioned signal C and signal a.
is supplied. /Age 1-25J5, this NOR gate 25, and an OAGOO 1-26 to which the output signals of ANDOGOO 1 to 24 are supplied in parallel. The output signal of the synchronization circuit 23 is the frame synchronization signal FR.
2 is supplied to the display interface circuit 10, and the output signal from the OR gate 26 is also supplied to the daily counter 7 as a rear signal CL.

Further, the number of bits of the n-ary counter 7 is set to a value that matches the maximum number of data lines to be displayed on the liquid crystal display 2.

Next, the operation of the circuit with the above configuration is shown in Figures 4 and 5.
This will be explained using timing gear 1 in the figure.

The timing chart in FIG. 4 is for a case where the number of data lines to be displayed on the liquid crystal display 2 is eight lines, as in the conventional case. C.P.
When a frame signal FRI with a period corresponding to these eight lines is input from U1, the rming signal optical generation circuit 19
Now, as shown in Figure 4, the same belief Qa as in Figure 2,
c are formed sequentially.

Since both signals a and C are supplied in parallel to the Android game 1-24 and the Noah game 1-25, the clock signal is sent from the Android games 1 to 24 at the rising edge of the frame signal FRI. A clear signal synchronized with the clock IgQφ is output from the NOR gate 25, and a clear signal synchronized with the clock IgQφ is output from the NOR gate 25 at the falling edge of the frame signal FR1. A clear signal C is output which is satisfied at each rising edge and falling edge of B).

The period of the frame signal FR1 corresponds to the period of the common signals COM1 to C10Mj (however, j-8), and in this one period, the clock signal φ is applied eight times, CPt
Since the output is from Jl, the count outputs JZ1 to Zj (j=3) of the n-ary counter 7 repeatedly change between O and 7, as in the case of FIG. 2.

As a result, the memory circuit 3 sequentially reads the data for the 8th line from the 0th line to the 7th line and supplies it to the display interface circuit 10. After this, the liquid crystal display 2 reads the data from the memory circuit 3. A display is made based on the data of 81T1.7 that was not output. 'The timing chart in FIG. 5 is for a case where the number of data lines to be displayed on the liquid crystal display 2 is 111, which is half of the above number. CPU 1 to this 4
When the frame signal FR1 having the period corresponding to the row is input, A in the timing signal optical regeneration 19 is input as described above.
From Agate 2G, the rear signal CL is as shown in Figure 5.
is output. At this time, the period of the frame (number FR1) is the common signal COMI or COMj (however, j-4).
corresponds to the period of
The advance count 71 is cleared in order to count one clock signal φ four times. However, -) Tezo's Karan 1 - Denofu changes repeatedly between 0 and 3 in decimal notation. As a result, in the memory circuit 3, 4 from the 0th row to the 3rd row
The data for the rows are sequentially read out and picked up by the display interface circuit 10. After this, the liquid crystal display 2 displays data based on the data for the four rows read out from the memory. In FIG. 5, Din is the input data supplied to the display interface circuit 10, and SEG is the segment I-signal output from the display ink-face circuit 10.

In this way, in the above embodiment circuit, the frame signal FR1
Clear signal CL at the rise and fall of
, the data can be displayed with various different numbers of lines (even if the number of lines is
There is no need to change the number settings.

In other words, since the hisomil number of the n-ary counter 7 can be fixed, the versatility can be increased.

[Effects of ZaL Light 1 As explained above, according to this light, during display, the counter circuit that specifies the row address of the memory circuit is cleared using the clock (g M Since this is done using a clear signal generated in synchronization with the above, it is possible to provide a display composition circuit with high versatility that can display the data on the number of lines of each line.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional circuit, Fig. 2 (1) shows the operation of the conventional circuit, and Fig. 3 is a circuit diagram showing an embodiment of this circuit. 15 and 5 respectively show the timing diagram of the above embodiment circuit. 1...CPIJ, 2...Liquid crystal display, 3...Storage circuit, 4...Row decoder, 5...・Ren de] 1g, 6...
・Data control circuit, 7...N-ary counter, 8...Selection circuit, 10...Display interface j name, 19...
・Timing signal generation circuit. Applicant's attorney Suzue Ni B

Claims (1)

[Claims] Storage means for storing data in segments 1 having a number of lines corresponding to the number of common signals, such as display means driven by a plurality of common signals and segment signals, respectively;
31 number means for specifying a row address of the storage means in accordance with the counting output using a clock signal as an argument; A frame signal having a cycle corresponding to the cycle of the plurality of common signals is supplied to the ceramic member 1 to the signal forming means for forming segment data, and is synchronized with the clock signal at the rise and fall of the frame signal, respectively. and a clear signal generating means for generating a clear signal for the 81 number means.