JPS6022360A - Manufacture of c-mos integrated circuit device - Google Patents

Abstract

PURPOSE:To easily form an extremely shallow source and drain diffusion region by a method wherein the thickness of the insulating film is differentiated between an n-channel transistor Tr and a p-channel Tr when a source and drain region is formed by implanting impurities. CONSTITUTION:After a gate polycrystalline silicon patterning has been performed, the thickness of the oxide films 4 and 5 on the source and drain region of a p-channel TrQ1 and an n-channel TrQ2 are differentiated with each other. As the atomic weight of arsenic is heavier than that of boron, a shallow junction can be formed with an injection energy of 50-100kev by forming a Q2 source and drain diffusion layer 9 by performing an ion implantation of arsenic and a Q1 source and drain diffusion layer 8 by performing an ion implantation of boron. Accordingly, if ions are implanted through the intermediary of an oxide film 5, impurities can be introduced into a shallow substrate. On the other hand, when a diffusion layer 5 is going to be formed, the projection flying distance of arsenic is made larger than that of boron when the same energy is applied, thereby enabling to introduce impurities into the region located in the vicinity of the interface of the oxide film 4 through the intermediary of the oxide film 8.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a complementary WMU8 integrated circuit device (hereinafter referred to as a C-MUS integrated circuit device) and a method for manufacturing the same. One known technique is to form source and drain regions using ion-implanted gold.Normally, when forming source and drain regions by ion implantation, the implantation energy is 50 to 150 keV and 500 keV is used.
Impurities are introduced into the substrate through an oxide film of ~1000A.The reason for performing ion implantation through an oxide film is that the ion implantation causes the crystals of the substrate to grow! 11. Impurities are removed from the knife knee during the post-implant annealing.
(Jut dtffuston) Sea! ') l
cj ;b to do. Incidentally, in order to achieve the above object, the thickness of the oxide film must be at least 100A or more.

In recent years, low acceleration ion implantation with an implant energy of 39 keys or less has been considered in order to reduce the overall region formation depth. However, when the implantation energy becomes low acceleration of 30 keys or less, it becomes difficult to focus the ion beam and the beam current decreases. Can't make it bigger. Therefore, when performing ion implantation at a high dose of rcro"ff1-2 or higher to form source and drain regions with a surface impurity concentration of 1020 to 10"fi-3, the implantation time is several minutes to
It becomes extremely long, several tens of minutes, and the throughput becomes extremely poor. -10,000, 15o.

If a shallow diffusion layer is to be formed through a thick oxide film of ~2000 Å, a high implantation energy of 300 keV or more must be used for impurities such as arsenic or phosphorous. For this reason, the temperature of the wafer rises during implantation, which impairs device customization, and the beam current cannot be increased due to limitations on high voltage and DC power supply capacity.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a CM (JS) integrated circuit device, which allows source and drain diffusion regions to be formed much shallower than ion implantation ICs with ease and with a high production ratio.

The present invention is characterized in that when forming the rcL9 source and drain regions by ion-implanting impurities through an insulating film, the thickness of the insulating film is made different between a P-channel transistor and an N-channel transistor.

Next, the present invention will be explained in more detail. Figure 1 is a diagram showing an embodiment of the present invention/C process V formed structure. That is, the gate polycrystalline silicon pattern The thickness of the oxide films 4 and 5 on the rear source/drain regions is different between the P channel transistor Q+ and the N channel transistor Q2.
The source/drain diffusion layer 9 of the P-channel transistor Q is made of arsenic, and the source/drain diffusion layer 8 of the P-channel transistor Q is made of arsenic. Assume that each is formed by boron ion implantation. Arsenic (due to its larger atomic weight compared to gboron, the implantation energy is 50 ~
It is possible to make a shallow compromise even with 100kev. For example, if the implantation energy is k5 (lkey), then the projected range of arsenic in the oxide film is
ge) oxide film 5 is formed, and the oxide film 5'f! : Through ion implantation, impurities can be introduced into the very shallow substrate near the interface between the substrate 2 and the oxide film 5. -10,000, Boron ion implantation 9 Ex, P channel transistor Ql source/drain diffusion layer 8? When formed, at the same energy, the projected range of boron and the curvature of the beam (xt) also increase. For example, when the implantation energy is 50 keys, the projected range of boron is ion implantation of boron through the entire film 8, so that the impurity can be introduced near the interface between the substrate 1 and the oxide film 4, as in the case of arsenic.

In this way, due to the structure in which the oxide film thicknesses of the source/drain regions of the N-channel transistor Q2 and the P-channel transistor Ql are different, the ion implantation energy 1
The entire source/drain diffusion layer can be formed in an extremely shallow portion of the substrate without using a low acceleration of 50 keys or less. Also, since there is no need for low acceleration, the beam current is high.
Even if the dose is to15cnt-2 or more 1c,'j, the implantation time can be shortened to within several tens of seconds.

An embodiment of the present invention is shown in FIGS. 2 to 4, and FIG. 2 shows a P well 2? - Forming field oxide film 6
selectively formed, and further gate polycrystalline silicon 3? FIG. 3 is a cross-sectional view after patterning. Next, as shown in FIG.
An oxide film 4 of λ is formed, and then the channel transistor region is masked using a photoresist 7 or the like, and the implantation energy is 5Qkev and the dose is 10~IO (1m-'7).
Ion-implant J boron to form P-type diffusion #8t-0
As shown in FIG. 4, after removing the photoresist 7, the P-channel transistor is covered with a photoresist 7'.
The oxide film 5 on the part that will become the source/drain region of the N-channel transistor is coated with a thickness of 1 (
Etch to 10-300A. Either wet etching or dry etching can be used as the etching method. Next, arsenic is implanted with an energy of 5Qkev at a dose of 1O1s-1016crrL-2vil-ion implantation to form the entire source and drain region 9. Next, after removing the photoresist 7, interlayer films, contact holes, electrodes, etc. are formed.

Second embodiment? This will be explained in the 5th to 71st sections. As shown in FIG. 5, after patterning the gate polycrystalline silicon three times, the entire oxide film 5 with a thickness of 100 to 300 Å is deposited on the source/drain regions, and a second film 10 is formed on the oxide film 5 with a thickness of 500 Å. ~
1000A is formed. The second film lO is a thermal nitride film, eV
D film, metal thin film layer, etc. can be used. Next, as shown in FIG. 6, the area where the source and drain regions of the N-channel transistor are to be formed is masked using a photoresist layer, etc., and boron ions are implanted into the area where the source and drain of the P-channel transistor are to be formed. Shape the diffusion layer 8 [
iE. The implantation energy should be selected so that the projected range is the interface VC between the oxide film and the substrate.Next, after removing the photoresist 7, the second film IO is removed by etching. Both etching methods are possible, but it is easier to remove by etching if the etching rate ratio between the oxide film 5 and the second film IO is as large as possible, and the etching conditions or the material of the second film are such that the etching rate ratio becomes large. Next, as shown in FIG. 7, after masking the P-channel transistor with a photoresist 7', arsenic is introduced into the region where the source and drain of the N-channel transistor are to be formed to form an n-type diffusion layer 9. Note that in the above two embodiments, after forming the source/drain diffusion NI of the HP channel transistor, the source/drain of the N channel transistor is formed, but it is also possible to reverse the formation order.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a structure formed according to an embodiment of the present invention. FIGS. 2 to 4 are cross-sectional views for explaining one embodiment of the present invention. FIGS. 5 to 7 are cross-sectional views for explaining other embodiments. ■--N-type semiconductor substrate, 2...P-well, 3...
Gate polycrystalline silicon, 4...0100-15 (IO
A oxide film, 5...100-300A oxide film, 6.
...Field oxide film, 7--Ion implantation mask such as resist, 8...P-type diffusion layer, 9...N-type diffusion layer,
lO... Aspirational film, (,: VD film, second layer of metal thin film, etc.)
Membrane agent Susumu Enhara, patent attorney

Claims (1)

[Claims] xP channel type MO8 transistor on semiconductor substrate and N
channel fiMO8) formed by forming a transistor
- In the method for manufacturing an MO8 integrated circuit device, when forming the source and drain regions of each MU8 transistor by ion implantation of impurities, each M
A method for manufacturing a C-MU8 integrated circuit device, characterized in that different impurities are ion-implanted through films of different thicknesses in an O8 transistor.