JPS60223150A - Resistance value adjusting method for multi-layered circuit substrate - Google Patents
Resistance value adjusting method for multi-layered circuit substrateInfo
- Publication number
- JPS60223150A JPS60223150A JP59078433A JP7843384A JPS60223150A JP S60223150 A JPS60223150 A JP S60223150A JP 59078433 A JP59078433 A JP 59078433A JP 7843384 A JP7843384 A JP 7843384A JP S60223150 A JPS60223150 A JP S60223150A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- resistance value
- adjusted
- layer
- resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 title abstract description 15
- 239000004576 sand Substances 0.000 claims abstract 3
- 239000000523 sample Substances 0.000 abstract description 2
- 238000010304 firing Methods 0.000 description 7
- 238000005488 sandblasting Methods 0.000 description 7
- 238000003475 lamination Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 238000009966 trimming Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002241 glass-ceramic Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000003303 reheating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/485—Adaptation of interconnections, e.g. engineering charges, repair techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/647—Resistive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、各層に抵抗を含む回路配線を施こした多層回
路基板の抵抗値調整方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for adjusting the resistance value of a multilayer circuit board in which circuit wiring including resistance is provided in each layer.
回路の高機能化、高集積化を図るため、厚膜ハイブリッ
ドエＣにおいても、単に抵抗体、コンデンサ、トランジ
スタ、ＩＣのみならず、多端子を有するＬＳＩ素子をも
搭載されたものが嘱望されている。ＬＥＴ工素子が搭載
されると、ＬＳＩ端子廻りの配線に占有される面積が多
くなり、また基板の入出力端子および各素子の端子との
配線レイアウトが極めて複雑化する。このようなＬＳＩ
素子搭載に伴う技術的不利益を解消するだめ、配線およ
び抵抗体が施こされた多数の回路層を積層して多層構造
の厚膜ハイブリットエＣが開発された。配線を多層内に
形成することは従来よシこの種の厚膜回路においても行
われておシ、実施する上で格別な困難性はない。しかし
ながら、抵抗体を各層毎に形成することは、下記のよう
な実施する上での問題が生じていた。In order to improve the functionality and integration of circuits, thick-film hybrid E-Cs are expected to be equipped with not only resistors, capacitors, transistors, and ICs, but also LSI elements with multiple terminals. There is. When LET elements are mounted, the area occupied by the wiring around the LSI terminals increases, and the wiring layout between the input/output terminals of the board and the terminals of each element becomes extremely complicated. This kind of LSI
In order to eliminate the technical disadvantages associated with device mounting, a thick film hybrid E-C with a multilayer structure was developed by laminating a large number of circuit layers each having wiring and resistors. Forming wiring in multiple layers has been conventionally performed in this type of thick film circuit, and there is no particular difficulty in implementing it. However, forming the resistor in each layer has caused the following problems in implementation.
即ち、この種の多層厚膜基板を製造する方法のうち、ガ
ラスセラミックスのグリーンンートに厚膜回路を印刷し
、これを積層した後焼成する方法は、微細な配線の形成
性および多層成形性が良好で、基板の小型化、集積化に
は最も適する。しかし、この方法は、多層回路基板の製
造工程において、各グリーンンートが各層毎に分離して
いる段階では、グリーンソート上に形成された抵抗体膜
は印刷、乾燥の状態［あるから、この状態で抵抗値の調
整を行うことは不可能である。また、各グリーンンート
を積層して焼成した後にあっては、内層の抵抗体に対し
ては、最上層の回路パターンが邪魔するため、従来、抵
抗体膜の抵抗値調整手段として通常用いられているレー
ザ或いはサンドブラストによっては、抵抗値調整を行う
ことができない。That is, among the methods for manufacturing this type of multilayer thick film substrate, the method of printing a thick film circuit on a glass-ceramic green board, laminating it, and then firing it has a high ability to form fine wiring and multilayer formability. It has good properties and is most suitable for miniaturization and integration of substrates. However, in this method, in the manufacturing process of multilayer circuit boards, at the stage where each green layer is separated, the resistor film formed on the green layer is in a printed and dry state [because it is in this state]. It is impossible to adjust the resistance value. In addition, after laminating and firing each green root, the circuit pattern on the top layer interferes with the resistor on the inner layer, so conventionally, it has not been used as a means for adjusting the resistance value of the resistor film. The resistance value cannot be adjusted by laser or sandblasting.
また、多層回路基板を製造する他の方法として、アルξ
す焼結基板上へ厚膜導体−厚膜抵抗体−厚膜絶縁体の印
刷、焼成を繰返し、アルミナ基板上へ抵抗体を多層化す
る方法が知られている。この方法によると、各層の抵抗
体膜が焼成されるので、その次の回路層が印刷されて積
層される前にレーザ、サンドブラストなどの手段を用い
て抵抗体の抵抗値を調整することが可能でおる。しかし
、積層以前に各層単独で抵抗体の抵抗値を調整しても、
次の回路層が印刷。In addition, as another method for manufacturing multilayer circuit boards,
A known method is to repeat printing and firing of a thick film conductor, a thick film resistor, and a thick film insulator on a sintered substrate to form a multilayer resistor on an alumina substrate. According to this method, the resistor film of each layer is fired, so the resistance value of the resistor can be adjusted using means such as laser or sandblasting before the next circuit layer is printed and laminated. I'll go. However, even if the resistance value of the resistor is adjusted individually for each layer before lamination,
The next circuit layer is printed.
焼成により積層されてゆく段階で、焼成時の再加熱など
の影響を受けて抵抗体の抵抗値が変動するため、精度の
高い抵抗値調整を行うことができない。各層単独での抵
抗値調整時に、以後の工程における抵抗値変化を見込ん
で抵抗値を調整しても、最終的に抵抗値のバラツキは±
２０係以上にもなシ、そのままでは実用回路基板として
供することができないので、積層後の最終工程でさらに
抵抗値の調整が必要となる。この抵抗値調整では、形成
される抵抗体の抵抗値が±５０％ばらつくため、これを
±５俤のばらつきに収めるためには、少なくとも、５０
％の抵抗値変化を可能としなければならない。At the stage of lamination through firing, the resistance value of the resistor changes due to effects such as reheating during firing, making it impossible to adjust the resistance value with high precision. When adjusting the resistance value of each layer alone, even if you adjust the resistance value in anticipation of changes in resistance value in subsequent processes, the final variation in resistance value will be ±
If the thickness is more than 20, it cannot be used as a practical circuit board as it is, so the resistance value needs to be further adjusted in the final step after lamination. In this resistance value adjustment, the resistance value of the formed resistor varies by ±50%, so in order to keep this variation within ±5 degrees, at least 50%
% resistance change must be possible.
結８− イｆ 九の多層回路基板形成手段を採るにして
も、最終工程において内層に形成された抵抗体の抵抗値
調整を可能とする多層回路基板の製造方法が開発されな
くては、抵抗体が多層内に形成された厚膜ハイブリッド
エＣの実現は困難である。Conclusion 8-f Even if the method for forming a multilayer circuit board in 9 is adopted, a method for manufacturing a multilayer circuit board that allows the resistance value of the resistor formed in the inner layer to be adjusted in the final process must be developed. It is difficult to realize a thick film hybrid film in which the body is formed in multiple layers.
尚、抵抗体の抵抗値調整手段としては、上記の他、抵抗
体に高電圧パルスを印加する方法が知られている。この
方法は、基板の最上層に適当な電極を形成しておけば、
最終工程においても内層に形成された抵抗体の抵抗値調
整を行うことが可能である。しかしながら、この方法は
レーザ或いはサンドブラストに比べて抵抗値の精度がか
なシ劣るため、任意の抵抗体の抵抗値調整に適用するに
は不適当である。In addition to the above, a method of applying a high voltage pulse to the resistor is known as a means for adjusting the resistance value of the resistor. In this method, if an appropriate electrode is formed on the top layer of the substrate,
Even in the final step, it is possible to adjust the resistance value of the resistor formed in the inner layer. However, this method is not suitable for use in adjusting the resistance value of any resistor because the accuracy of the resistance value is inferior to that of laser or sandblasting.
本発明の目的は、上記従来技術の欠点を除き各層の抵抗
体の抵抗値を所定の精度で設定できるようにした多層回
路基板の抵抗体調整方法を提供するにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for adjusting a resistor of a multilayer circuit board, which eliminates the drawbacks of the prior art described above and allows the resistance value of the resistor of each layer to be set with a predetermined accuracy.
本発明は、上記の目的を達成するために、最上層に、レ
ーザ或いはサンドブ２ストニよって抵抗値を調整するこ
とを要する抵抗体を形成し前記最上層以外の内層に、高
電圧パルスを印加することによって調整可能な抵抗体を
形成し、前記最上層に形成された抵抗体の抵抗値をレー
ザ或いはサンドブラストによって調整し、前記内層に形
成された抵抗体の抵抗値を高電圧パルスを印加すること
によって調整することを特徴とするものである。In order to achieve the above object, the present invention forms a resistor whose resistance value needs to be adjusted by a laser or sandblast in the top layer, and applies a high voltage pulse to the inner layers other than the top layer. forming an adjustable resistor by adjusting the resistance value of the resistor formed in the top layer by laser or sandblasting, and applying a high voltage pulse to adjust the resistance value of the resistor formed in the inner layer; It is characterized by adjustment by.
以下、本発明の実施例を図面について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例を示す多層回路基板の断面図
、第２図はその積層前の各層の断面図である。FIG. 1 is a sectional view of a multilayer circuit board showing an embodiment of the present invention, and FIG. 2 is a sectional view of each layer before lamination.
マス、ホウクイ酸鉛ガ２ス粉末とアルミナ粉を６：４の
割合で混合した混合物を、通常のセラミックスゲリーン
シートの成型と同様のブレード法によるキャスティング
で、厚さ０．５ｍのグリーンンートを形成する。次いで
、これを第２図に示すように所定の寸法に切断し、絶縁
性印刷基板１，２，３．４を作成する。次いでと・の絶
縁性印刷基板１，２，３．４の所定の位置に、上下方向
の導通路（グイアホール）を形成−するためのスルーホ
ール１ａ 、 ２ａ 、 ５ａ、 ４ａをパンチングし
、最下層の絶縁性印刷基板４を除く他の絶縁性印刷基板
１，２．３のスルーホール１ａ 、 ２ａ 、 ３ａに
Ａｙ、Ｐｄ系の導体ペーストをメタルスクリーンマスク
によって印刷、充填しグイγホールＩＡ、２Ａ、５Ａを
形成する。次いで前記各絶縁性印刷基板１，２，３．４
に所定の回路パターン・を形成したスクリーンマスクに
より、配線ＩＣ，２Ｃ，３Ｃ，４Ｃ，および抵抗体用電
極１ｄ、 ２ｉ 、３ｄ、 ４ｉ、および抵抗体１ｃ、
、２８５ｍ 、 ４６を形成する。A mixture of mass, lead borosinate gas powder, and alumina powder in a ratio of 6:4 was cast using the blade method similar to the molding of ordinary ceramic gelene sheets to form green sheets with a thickness of 0.5 m. Form. Next, as shown in FIG. 2, this is cut into predetermined dimensions to create insulating printed circuit boards 1, 2, 3.4. Next, through holes 1a, 2a, 5a, 4a for forming vertical conduction paths (guia holes) are punched at predetermined positions of the insulating printed circuit boards 1, 2, 3.4, and the bottom layer is The through holes 1a, 2a, 3a of the other insulating printed boards 1, 2.3 except the insulating printed board 4 are printed and filled with Ay and Pd based conductive paste using a metal screen mask to form the γ-holes IA, 2A. , 5A. Next, each of the insulating printed substrates 1, 2, 3.4
Wiring ICs, 2C, 3C, 4C, resistor electrodes 1d, 2i, 3d, 4i, and resistor 1c, using a screen mask with a predetermined circuit pattern formed thereon.
, 285m, forming 46.
この場合、最上層の絶縁性印刷基板ＩＫ影形成れる抵抗
体１らとしては、抵抗値調整パルスを印加しても高１圧
が発生せず、大きな抵抗値変化を得ることのできない、
抵抗値の低い抵抗体、および高精度の抵抗値調整を要求
される抵抗体、および部品搭載後に抵抗値の調整をする
ことを要する機能トリミング用の抵抗体が形成される。In this case, the resistor 1 formed by the uppermost insulating printed board IK does not generate a high voltage even when a resistance adjustment pulse is applied, and cannot obtain a large change in resistance value.
A resistor with a low resistance value, a resistor that requires highly accurate resistance value adjustment, and a resistor for functional trimming that requires resistance value adjustment after components are mounted are formed.
本実施例では、前記低抵抗値の抵抗体として、ソート抵
抗が１００Ω／口の抵抗体ペーストが用いられ、前記機
能トリミング用の抵抗体として、１０乙の抵抗体ペース
トが用いられた。ｌだ、前記内層の絶縁性印刷基板２．
３゜４に形成される抵抗体２ｍ 、６− 、４ｇとして
は、抵抗調整パルスを印加することによって大きな抵抗
値変化率を得ることができる抵抗体、および比較的高精
度の抵抗値調整を要求されない抵抗体が形成される。本
実施例では、前記内層の絶縁性印刷基板２ 、３ 、４
に形成される抵抗体２４ 、３ｇ 、 ４ｇとして、シ
ート抵抗が省０１０．１０ｋｎ７Ｉ：ｌ、 １ｏｏ”１
０の抵抗体ペーストが、ＦＦｉ定の回路設計に従って、
圧意に用いられた。In this example, a resistor paste with a sort resistance of 100Ω/hole was used as the low resistance value resistor, and a resistor paste with a sort resistance of 10Ω/hole was used as the resistor for functional trimming. 1. The inner layer of the insulating printed substrate 2.
The resistors 2m, 6-, and 4g formed at 3°4 require resistors that can obtain a large resistance change rate by applying a resistance adjustment pulse, and require relatively high-precision resistance adjustment. A resistor is formed that does not In this embodiment, the inner layer insulating printed substrates 2, 3, 4
As the resistors 24, 3g, and 4g formed in
0 resistor paste according to the FFi constant circuit design,
It was used for coercion.
前記抵抗体１ｍの形成と同時に、前記最上層の絶縁性印
刷基板１には、抵抗値調整用のグローブ端子５が形成さ
れ、このプローブ端子５や抵抗体電極１ｄを除く絶縁性
印刷基板１の印刷面全体に、絶縁＄６が印刷形成場れる
。次いで上記のように形成された各絶縁性印刷基板１゜
２．３．４を位置合せして積み重ね、４０宛、１０１Ｊ
−ｔ＋ −２０分間のホットプレス下で一体化スる。At the same time as the resistor 1m is formed, a globe terminal 5 for adjusting the resistance value is formed on the uppermost layer of the insulating printed board 1. Insulation $6 is applied to the entire print surface. Next, each insulating printed circuit board 1゜2.3.4 formed as described above was aligned and stacked, 40 pieces, 101J.
-t+ - Integrate under hot press for 20 minutes.
次いで、これを９００°０−１５分間の高温域を有する
厚膜ベルト炉によって焼成し、第１図に示すような、抵
抗体が多層に形成された多階回路基板を得る。Next, this is fired in a thick film belt furnace having a high temperature range of 900° for 0 to 15 minutes to obtain a multi-layer circuit board on which resistors are formed in multiple layers as shown in FIG.
このように形成された多層回路基板の各抵抗体は、次の
ように調整される。前記最上層の絶縁性印刷基板１に形
成された抵抗体１＃の抵抗値を、レーザ或いはサンドブ
ラストによって調整し、また前記内層の絶縁性印刷基板
２．６゜４に形成された抵抗体２ｇ 、 ３ｇ 、 ４
１の抵抗値を個々の被調整抵抗体にプローブ端子５から
グイアホール１ｈ、２ｂ、５ｂ、および抵抗体用電極２
ｄＸ、ｄ 、 ４ｄを介して個別的に高電圧・くルスを
印加することによって調整する。Each resistor of the multilayer circuit board thus formed is adjusted as follows. The resistance value of the resistor 1# formed on the uppermost layer insulating printed board 1 is adjusted by laser or sandblasting, and the resistor 2g formed on the inner layer insulating printed board 2.6°4, 3g, 4
The resistance value of 1 is connected to each resistor to be adjusted from the probe terminal 5 to the Guia holes 1h, 2b, 5b, and the resistor electrode 2.
Adjust by applying high voltage pulses individually through dX, d, and 4d.
抵抗体２□、３ｍ、４ｇの抵抗値は、印加されるパルス
の′屯田、パルス幅、印加回数によって変動する。この
ため、抵抗体２ｇ 、 ５ｇ 、 ４１の調整に当って
は、予め被調整抵抗体の７−ト抵抗抵抗値、抵抗体の形
状、抵抗値と目標値との差（トリハング量）から最適条
件をめておき、この条件に従って抵抗値の調整を行う。The resistance values of the resistors 2□, 3m, and 4g vary depending on the width of the applied pulse, the pulse width, and the number of times of application. Therefore, when adjusting the resistors 2g, 5g, and 41, the optimum conditions are determined in advance based on the resistance value of the resistor to be adjusted, the shape of the resistor, and the difference between the resistance value and the target value (trihang amount). Adjust the resistance value according to this condition.
印加されるパルスとしては、抵抗体に印加される電圧の
電界強度が０〜５ ／顛、パルス幅５００μ寞以内、パ
ルス回数１０２回以内が多用される。また、この抵抗値
調整パルスの印加方法としては、第３図に示すように、
第１回目のパルス印加で被ｖＩ４整抵抗体の抵抗値が目
標値の＋１０チ以内になるような条件でパルスを印加し
、以後第２回目以降のパルス印加で目標値となるような
条件でパルスを印加する。このようなパルス印加方法を
採るのは、上記のように予め最適パルス条件をめておい
ても、抵抗値の予測変化率は実際の抵抗値の変化率に対
して±２０％の誤差が見込まれるため、過剰パルス負荷
による抵抗値の過小化を防止するためである。本実施例
では、第１回目に電界強度２ｋｖ／、パルス幅２０μ式
のパルスを印加し、第２回目乃至第１０回目に電界強度
１ ／、パルス幅２μ減のパルスが印加されるように、
条件設定した。As for the pulses to be applied, the electric field strength of the voltage applied to the resistor is often 0 to 5/2, the pulse width is 500 μm or less, and the number of pulses is 102 times or less. In addition, as a method of applying this resistance value adjustment pulse, as shown in FIG.
Apply a pulse under conditions such that the resistance value of the resistor vI4 becomes within +10 degrees of the target value in the first pulse application, and then under conditions such that the resistance value of the vI4 resistance element becomes within +10 degrees of the target value in the second and subsequent pulse applications. Apply pulse. The reason for adopting this pulse application method is that even if the optimum pulse conditions are determined in advance as described above, the predicted rate of change in resistance value is expected to have an error of ±20% from the actual rate of change in resistance value. This is to prevent the resistance value from becoming too small due to excessive pulse load. In this example, a pulse with an electric field strength of 2 kV/ and a pulse width of 20 μ is applied in the first time, and a pulse with an electric field strength of 1 / and a pulse width of 2 μ is applied in the second to 10th times.
Conditions were set.
また、本実施例では、前記最下層の絶縁性印刷基板１に
形成された抵抗体１−のうち、１００／。Further, in this embodiment, among the resistors 1- formed on the lowermost insulating printed board 1, 100/.
の抵抗ペーストによる抵抗体は、通常のレーザトリばン
グによシ抵抗値を調整することによｐ±１チの精度を得
た。また、前記最上層の絶縁性印刷基板ＩＶｃ形成され
た抵抗体１ｅのうち、機能トリミング用の抵抗体は、Ｌ
ＳＩ、コンデンサなどの部品（図示せず）を搭載後、回
路を動作させながら所定の特性を得るよう、レーザによ
り抵抗値を調整する。The resistor made of the resistor paste obtained an accuracy of p±1 inch by adjusting the resistance value by ordinary laser tribbing. Furthermore, among the resistors 1e formed on the uppermost insulating printed board IVc, the resistors for functional trimming are L
After mounting components such as an SI and a capacitor (not shown), the resistance value is adjusted using a laser to obtain predetermined characteristics while operating the circuit.
尚、上記実施例では、抵抗体を多層に形成する多層回路
基板の形成方法として、ガラスセラばツクスのグリーン
シートに厚膜回路を印刷しこれを積層して焼成する方法
（グリーンシート法）のみ示したが、本発明の要旨はこ
れに限定されるものではなく、レーザ或いはサンドブラ
ストによって抵抗値が調整されるべき抵抗体（たとえば
、１００／。抵抗体ペーストで形成される抵抗体）を最
上階に形成するレイアウトをとれば、アルミナ焼結基板
上に厚膜回路を繰り返し印刷、焼成する方法（乾式法）
ＶＣよっても実施’５Ｊ能である。In the above embodiments, only a method (green sheet method) of printing a thick film circuit on a glass ceramic green sheet, laminating and firing the same is shown as a method for forming a multilayer circuit board in which resistors are formed in multiple layers. However, the gist of the present invention is not limited thereto, and a resistor whose resistance value is to be adjusted by laser or sandblasting (for example, a resistor formed with a 100% resistor paste) is placed on the top floor. If a layout is adopted, thick film circuits are repeatedly printed and fired on an alumina sintered substrate (dry method).
VC is also capable of implementing '5J'.
表−１１Ｃ，グリーンシート法および乾式法によって多
層に形成された抵抗体を、従来技術および上記実施例に
よって調整したときの、抵抗値のバラツキの比較を示す
。Table 11C shows a comparison of variations in resistance values when resistors formed in multiple layers by the green sheet method and the dry method were adjusted by the conventional technology and the above embodiments.
表−１
表−ＩＫ明らかなように、上記実施例の多層回路基板の
抵抗体調整方法によると、従来調整不可能であったグリ
ーンシート法によって形成される内層の抵抗体の抵抗値
調整が可能とな＼シしかも、その場合の抵抗値のバラツ
キは±５１以内に収まシ、実用上間亀のない多層回路基
板を得られることが判る。Table-1 Table-IK As is clear, according to the method for adjusting the resistor of the multilayer circuit board of the above embodiment, it is possible to adjust the resistance value of the resistor of the inner layer formed by the green sheet method, which was previously impossible to adjust. Furthermore, it can be seen that the variation in resistance value in this case is within ±51, and a multilayer circuit board with no gaps can be obtained in practice.
また、乾式法によって形成される内層の抵抗体の抵抗値
のバラツキが±２０％から±５チに低下し、実用的な多
層回路基板となっていることが判る。Furthermore, it can be seen that the variation in the resistance value of the inner layer resistor formed by the dry method has been reduced from ±20% to ±5 inches, making it a practical multilayer circuit board.
また、最上層に形成された抵抗体についてはグリーンシ
ート法、乾式法とも、レーザ若しくはサンドブラストに
よって抵抗値の調整が可能であシ、このため、抵抗値の
ノ（ラソキが±１チという高精度に調整することができ
る。In addition, the resistance value of the resistor formed on the top layer can be adjusted by laser or sandblasting with either the green sheet method or the dry method. can be adjusted to
以上説明したように、本発明によれは、各層に配置され
た抵抗体の抵抗値を、積層焼成後に所望の精度で設定す
ることができるものであって、抵抗値調整作業も簡略化
されて、高集積小型の多層厚膜ノ・イブリットエＣ基板
の適用範囲を拡大することが可能となる。As explained above, according to the present invention, the resistance value of the resistor arranged in each layer can be set with desired accuracy after lamination firing, and the resistance value adjustment work is also simplified. This makes it possible to expand the scope of application of highly integrated, compact, multilayer, thick film, hybrid C substrates.
第１図は本発明の一実施例を示す多層回路基板の断面図
、第２図はその積層前の各層の断面図、第３図は高電圧
パルスの印加に伴なう抵抗値変化の一具体例を示すグラ
フ図である。
１．２，３．４・・・絶縁印刷基板
１ａ、２ａ、３ａ ・・・スルーホール１ｂ、 ？ 、
５４ ・・・グイアホール１ｃ 、 ２Ｇ 、 ３ｃ
、 ４Ｇ・・・配線ｉｊ 、 ２ｄ 、 ５ｄ 、
４ｄ・・・抵抗体用電極Ｉｇ 、 ２ｍ 、 ５− 、
４ｍ ・・・抵抗体５・・・グローブ端子
６・・・絶縁層
第 １ 図
（＝）
ｉｐ、 ｚＩ）、 ８ｈ
（イ）
第２図Fig. 1 is a cross-sectional view of a multilayer circuit board showing an embodiment of the present invention, Fig. 2 is a cross-sectional view of each layer before lamination, and Fig. 3 is a diagram showing a change in resistance value due to application of a high voltage pulse. It is a graph diagram showing a specific example. 1.2, 3.4...Insulated printed circuit board 1a, 2a, 3a...Through hole 1b, ? ,
54...Guia Hall 1c, 2G, 3c
, 4G...Wiring ij, 2d, 5d,
4d...Resistor electrode Ig, 2m, 5-,
4m...Resistor 5...Globe terminal 6...Insulating layer Fig. 1 (=) ip, zI), 8h (A) Fig. 2
Claims (1)
された多層回路基板の抵抗値調整方法において、最上層
に低い抵抗値の抵抗体および高精度の抵抗値設定が必要
な抵抗体を配置し内層に高い抵抗値の抵抗体および抵抗
値に高精度を要求されない抵抗体を配置し、前記最上層
の抵抗体の抵抗値をレーザあるいはサンドグ２ストによ
って調整するとともに、前記内層の抵抗体の抵抗値を高
電圧パルスの印加によって調整することを特徴とする多
層回路基板の抵抗値調整方法。In the resistance value adjustment method for a multilayer circuit board that has a multilayer structure and has circuit wiring including a resistor in each layer, a resistor with a low resistance value in the top layer and a resistor that requires highly accurate resistance value setting are used. A resistor with a high resistance value and a resistor whose resistance value does not require high accuracy are arranged in the inner layer, and the resistance value of the resistor in the uppermost layer is adjusted by a laser or a sand 2 strike, and the resistance of the inner layer is adjusted. A method for adjusting the resistance value of a multilayer circuit board, the method comprising adjusting the resistance value of the body by applying a high voltage pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59078433A JPS60223150A (en) | 1984-04-20 | 1984-04-20 | Resistance value adjusting method for multi-layered circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59078433A JPS60223150A (en) | 1984-04-20 | 1984-04-20 | Resistance value adjusting method for multi-layered circuit substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60223150A true JPS60223150A (en) | 1985-11-07 |
Family
ID=13661904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59078433A Pending JPS60223150A (en) | 1984-04-20 | 1984-04-20 | Resistance value adjusting method for multi-layered circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60223150A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06131085A (en) * | 1990-04-30 | 1994-05-13 | Motorola Inc | Precise terminating circuit |
-
1984
- 1984-04-20 JP JP59078433A patent/JPS60223150A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06131085A (en) * | 1990-04-30 | 1994-05-13 | Motorola Inc | Precise terminating circuit |
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