JPS60222937A - Computer device - Google Patents

Abstract

PURPOSE:To clear up easily causes of abnormality of a CPU by providing a counter set signal generating means, a monitor program executing means, a start means of this executing means, an information storage means, and an information erasing means. CONSTITUTION:When a CPU1' becomes abnormal, a monitor timer 2 expires, and the CPU1' executes an initial start program by the momentary output of a CPU reset signal B. Various information of a monitor program are stored in an emergency information area of a RAM, and various information of the monitor program are erased, and thereafter, execution of the monitor program is started. Simultaneously, the output of the monitor timer 2 is counted by a counter 3. This operation is repeated each time when the CPU1' becomes abnormal; and when the number of times of abnormality occurrence reaches a prescribed value, the counter 3 outputs an output, and the CPU reset signal B is outputted continuously from an OR gate 4, and the CPU1' is reset and is stopped. Various information of the monitor program are stored in a different area each time when abnormality occurs.

Description

[Detailed description of the invention] This invention relates to a computer device.

A conventional computer device, as shown in FIG.
It is composed of a U (central processing unit) 1, a monitoring timer 2, a detection number counter 3, and an OR gate 4. The CPUI receives an instantaneous timer recent signal A during the monitor program.
When the power is turned on or when the CPU IJ set signal is input, the initial start program is executed, and then the monitor program is executed. An instantaneous counter reset signal C is generated when the power is turned on. Monitoring timer 2 uses timer reset signal A to set the timer time.
The timer recent signal A is applied to the reset input terminal. Detection number counter 3
The counter reset signal C from the CPUI is applied to the reset input terminal, and the OR gate 4 gives the Cf)U reset signal B to the CPUI when the monitoring timer 2 times up or when the detection number counter 3 counts a predetermined number. ing.

The operation will be explained. First, when the power is turned on, the CPU
1 erases various information of the monitor program by executing an initial start program as shown in FIG. 2, and then starts executing the monitor program. At this time, a counter reset signal C is output from the CPUI and the detection number counter 3 is reset.

Then, the monitoring timer 2 starts monitoring after the power is turned on, and the detection number counter 3 starts counting.

Now, if the CPU is operating tightly, the timer reset signal A is periodically output from the CPU1, and the monitoring timer 2
is reset to 11;
I continues the real fi of the monitor program.

If the CPU 1 becomes abnormal due to defective parts or a faulty program, the timer reset signal is no longer output, and as a result, the monitoring timer 2 times up and the OR gate 4
From CP tJ reset signal signal reactor is instantaneously output from C
I) CIl[Every time Il executes the initial start program, various information of the monitor program is erased, and then execution of the monitor program is started. Also, at this time, a detection number counter 3 counts the output of the monitoring timer 2. The above operation is repeated every time the CPUI becomes abnormal, and when the number of abnormalities reaches a predetermined number, the detection number counter 3 generates an output.
The CP error signal B is continuously outputted from the OR gate 4 and applied to the CPUI, and CI) U1 is reset and its state is maintained. In other words, the CPUI will stop. If the power is turned off and turned on again, the detection counter 3 is reset and the CPU becomes operational.

In such a conventional configuration, when the CPU 1 executes the initial start program, various information of the monitor program is erased, and as a result, abnormalities are repeated and the CPU
It was not easy to find the cause of the abnormality when the UI stopped operating.

Therefore, an object of the invention is to provide a computer device that can easily determine the cause of abnormality in a CPU.

The computer device of this invention, as shown in FIG.
A supervisory timer 2 that is reset by an instantaneous timer recent signal and generates an instantaneous CPU reset signal when time-up; and an instantaneous CPU reset signal that is reset by an instantaneous counter reset signal and output from the supervisory timer 2. a detection number counter 3 that counts the number of occurrences and generates a continuous CPU reset signal when the value reaches a predetermined value; and a detection number counter 3 that generates the instantaneous counter reset signal when the power is turned on. executing a monitor program incorporating a counter reset signal generating means IA to be applied to the CPU reset signal and a function of periodically generating the instantaneous timer reset signal; and executing the monitor program in response to the generation of the CPU reset signal. Monitor program execution means IB that stops and resets
Then, each time the CPU reset signal 1iii disappears, the various information of the monitor program is sequentially stored in different areas of the memory.
\Information storage means IC for storing, information erasing means 11 for erasing various information of the monitor program in response to the completion of the operation of this information storage means]; The present invention is characterized in that it is configured to include a start means IB for starting the monitor program execution means in response to completion of the operation.

An embodiment of the present invention will be described based on FIGS. 3 to 5. As shown in FIG. 3, this computer device has a CPU', a monitoring timer 2. It consists of a detection number counter 3 and an OR gate 4, among which a monitoring timer 2. Detection counter 3 and OR gate 4
is the same as that in Figure 1. The CPUI' has a built-in function that periodically generates an instantaneous most recent signal A during the monitor program.
An initial start program is executed when the reset signal signal is input, and an instantaneous counter reset signal is generated when the power is turned on.

The operation will be explained. First, when the power is turned on, the CPU
I' executes an initial start program as shown in FIG. This initial start program first determines whether this execution is due to an instantaneous CPU reset signal A. In this case, since the initial start program is executed when the power is turned on, the determination result is No, and after erasing various information of the monitor program, execution of the monitor program is started. At this time, an instantaneous counter reset signal C is output from the CPUI' and the detection number counter 3 is reset.

Then, the monitoring timer 2 starts monitoring after the power is turned on, and the detection number counter 3 starts counting.

Now, if CPU1' is operating in the royal palace, an instantaneous timer reset signal A is periodically output from CPU1',
The monitor timer 2 is reset before it times up, the monitor timer 2 never times up, the CPU reset signal is not input from the OR gate 4, and the CPU
continues running the monitor program.

If the CPU' becomes abnormal due to defective parts or a faulty program, the timer reset signal is no longer output to Shinji, and as a result, the monitoring timer 2 performs time amplification, and the OR gate 4 outputs the CPU reset signal from time to time.
PUI' is entered and CPUI' executes the initial start program.

This initial start program first starts with this execution
Determine whether the U reset signal is compared to the signal. In this case, since it was caused by the CPU recent signal A, the judgment result was YES, and the various information of the monitor program was stored in the emergency information area MA of the RAM shown in Fig. 5, and then the various information of the monitor program was erased. after,
Start execution of the monitor program. Also, at this time, a detection number counter 3 counts the output of the monitoring timer 2. The above operation will be repeated every time CPUI' becomes abnormal. In this case, various information of the monitor program is sequentially stored in different areas each time an abnormality occurs. When the number of abnormal occurrences reaches a predetermined number, the detection number counter 3 generates an output, and the OR gate 4 continuously outputs the CPU reset signal and adds it to the CPUI'.
PUI' is reset and its state is maintained. In other words, the CPUI' will be stopped. When the power is turned off and then turned on again, the detection number counter 3 is reset and the CPUI' becomes operational.

Note that the timer time of the monitoring timer 2 and the setting values of the detection number counter can be arbitrarily set by hardware.

As a result of this configuration, when an abnormality occurs, various information of the monitor program at that time is stored in the emergency information area MA.
When ui' stops, if the operator uses a depack tool to read various information of the monitor program stored in the emergency information area MA and analyzes it, the cause of the abnormality can be easily determined.

Note that the various information of the monitor program stored in the emergency information area MA can be deleted by an operator's operation.

As described above, according to the computer device of the present invention,
This has the effect that the cause of CPU abnormality can be easily determined.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional computer device, Fig. 2 is a flowchart showing its operation, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 shows its operation. Flowchart, Figure 5 is a configuration diagram of the emergency information area,
FIG. 6 is a block diagram showing the configuration of the present invention. 1'... CPU, 2... Monitoring timer, 3... Detection number link, 4... OR gate, IA... Counter readout 1-signal generation means, IB... Monitor program execution means, IC. ...Write down the information? Means, ID...
Information erasure means, IE...Start means Figure 1? lI2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] A supervisory timer that is reset by an instantaneous timer recent signal and generates an instantaneous CPU reset signal when time-up; and an instantaneous C that is reset by an instantaneous counter reset signal and output from the supervisory timer.
A detection frequency counter that counts the number of times a PU reset signal appears and generates a continuous CPU reset signal when the value reaches a predetermined value, and a detection frequency counter that generates the instantaneous counter reset signal when the power is turned on and detects the number of times the CPU reset signal is detected. A monitor program incorporating means for generating a counter reset signal to be applied to a counter and a function of periodically generating the instantaneous timer reset signal is executed, and execution of the monitor program is stopped in response to generation of the CPLI recent signal. monitor program execution means for resetting the CPU;
an information memory 1Ω for sequentially storing various information of the monitor program in specific areas of the memory each time a reset signal is generated;
means, information erasing means for erasing various information of the monitor program in response to the completion of the operation of the information storage means, and starting the monitor program execution means when the power is turned on and in response to the completion of the operation of the information erasing means. A computer device comprising: a start means for starting the computer;