JPS61103251A - Debug device for microprocessor system - Google Patents

Abstract

PURPOSE:To faciliate an analysis for fault factors by detecting automatically a fact that a module runs or has access out of an address range and outputting visually the addresses and the data bus information obtained before and after an abnormal operation is produced. CONSTITUTION:A memory 26 supplies a signal ADD1 of address information to a signal line 11 from a microprocessor system 1 to be monitored and then a signal DATA1 of data bus information onto a signal line 12 respectively. These signals are stored temporarily according to the value on a signal line 42. Both signals ADD1 and DATA1 are always written while the system 1 has a normal operation. Then the write signal on the line 42 inhibits the operation of the system 1 though an AND gate 27 in case a fault signal is inputted onto a signal line 38 owing to the generation of a fault. Then a writing action is discontinued. A CPU2-28 knows that the information is supplied to the line 38 via an input/output interface 31 and delivers designations to the memory 26 for addresses from the head one to the final one. Then data are read out and outputted to a typewriter 6.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a program debugging device for a microprocessor system built into a facsimile machine.

(Prior Art) In conventional device-embedded microprocessor systems, there is a function to detect abnormal conditions associated with the execution of user application programs such as large computer systems, such as deviation from a specified driving range or access prohibited. There are no detection functions such as writing to the area and extracting operations.

(Problems to be Solved by the Invention) Therefore, in the early stages of system development, if a failure occurs (due to a latent bug in a program), there is no means to immediately respond to the failure.

In particular, when the frequency of occurrence of failures is low, searching for the cause of the failure requires a considerable amount of time.

Tsutomu: 'The purpose of the present invention is to define a running address range and an access address range for each module of a program divided into modules, monitor the corresponding address path information during the regular operation period of each module, and determine the address path. It temporarily stores information and data path information and automatically detects when driving or accessing outside of the specified address range.
A microprocessor system configured to eliminate the above drawbacks and easily analyze the cause of failures by reading address path information and data path information before and after an abnormal operation occurs, and outputting it to a typewriter for visualization. The purpose is to provide a debugging device.

(Means for Solving the Problems) A microprocessor system debugging device according to the present invention provides a plurality of microprocessor system debugging devices for controlling the operation of incorporated devices by running inside or accessing a defined memory area. The system is connected to a microprocessor system incorporating a program module and a monitor module having an execution management function for multiple program modules, and is equipped with an address monitoring circuit, a memory circuit, and a control circuit. It is composed of

The address monitoring circuit inputs address range information indicating the running address range and access address range of the program module and the address path information of the microprocessor system, which are output before the program module starts up, from the monitor program, and monitors the program module. This is for monitoring the address path information while the module is running and outputting a trigger signal if the address path information deviates from the address range indicated by the address range information.

The memory circuit always inputs and continuously stores address path information and data path information from the microprocessor system, and when a trigger signal occurs, it stores a predetermined amount of address path information and data path information from the time of generation. This is to write the data and stop the operation after the writing is completed.

The control circuit reads address path information and data path information inside the memory circuit after the write operation of the memory circuit is stopped, outputs the information to the output device, and also monitors the state of the address monitoring circuit and controls the memory circuit. It is the ninth one.

(Example) Next, an example of the present invention will be described with reference to some drawings. FIG. 1 is a block diagram showing an embodiment of a microprocessor system debugging device according to the present invention. In FIG. 1, 1 is a part of a microprocessor system for device control that can monitor the running status of a program using an i microprocessor system debug device, 2 is a microprocessor system debug device according to the present invention, and 3 is an address monitoring circuit. , 4 is a memory circuit, 5 is a control circuit, and 6 is a typewriter (TTY) for recording address path/data path information outputted from the program debugging device 2 onto a signal line 37. 7 is the microprocessor (OPUI)
, 8 is a program memory (f'LOMl). The microprocessor 7 controls the operation of the incorporated device according to the program stored in the program memory 8. The program memory 8 is divided into a plurality of modules, and includes a device control program that defines a running address range and an access address range, as well as a monitor program that has a function to execute and manage this program.
cvru. The monitor program activates the device control program modules in a prescribed order. Prior to activation of a device control program module, address range information consisting of running address range information and access address range information of the corresponding program module is output from the program memory 8. In this embodiment, it is assumed that the running address range and the access address range are adjacent to each other, and the address range information is the maximum running address or the access address information (AD
MAX) and, 1-esi”°)-
0ゝ small! Mt*H7/-h "7 do" information (person D MIN
) is output. 9 is a temporary storage memory (RAM l) consisting of a random access memory used as a work area for the microprocessor 7; 1o is a signal line 1;
This is an output interface for outputting address range information on 5 and 16. 11, 13, and 14 are address path information (ADDI) signal lines, read pulse signal lines, and write pulse signal lines output from the nine microprocessor 7, respectively.

Reference numeral 12 indicates data path information input/output to/from the microprocessor 7 (signal line DATAi; 17 indicates data path information input/output to/from the microprocessor 7;
A first comparison circuit (OOMPl) 18 monitors whether the ADMAX value on the signal line 16 is exceeded or not; This is a second comparator circuit (OOMPz) for monitoring. If the running or access address of the microprocessor 7 deviates from the range defined by the ADMAX l value on the signal line 15 and the ADMIN value on the signal line 16, a comparison signal is sent to the signal line 40 or 41. is output. 19 is an OR gate for calculating the logical sum of the read pulse from the microprocessor 7 onto the signal line 13 and the write pulse from the signal line 14, and the logical sum is output onto the signal line 42. 1st f? and the signal line 42 is connected to the output control terminal in the second comparator circuit 17 and 18.
is connected, and the comparison result is output onto signal lines 40 and 41 only when address path data is determined. 20 is an OR gate for calculating the logical sum of comparison signals on signal lines 40 and 41, and if either one of the signals is input, a trigger signal is output on signal line 43. 21 is a latch circuit for latching the trigger signal on the signal line 43, 22 is an AND gate, and 23 is a counter. The output of the latch circuit 21 is input to the AND gate 22 together with the signal on the signal line 42, and
The output of 2 is input to the counter 23 via the signal line 44. The counter 23 defines the write amount from when a trigger signal is generated on the signal line 43 to when the write operation between the address on the ADDi signal line ll leading to the memory circuit 4 and the data on the DATAI signal line 12 is stopped. It is for. The counter 23 calculates the value on the signal line 44 which is the logical sum of the read pulse on the signal line 13 and the write pulse on the signal line 14 by the microprocessor 7 after the trigger signal on the signal line 43 is turned on. Count. The counter 23 outputs a carry signal onto the signal line 45 after counting the signals on the signal line 44 by a prescribed number. The carry signal on the signal line 45 is latched by the latch circuit 24 and outputted onto the signal line 38 as a count end signal. The count value on the signal line 44 for the counter 23 is set by count information sent from the control circuit 5 onto the signal line 36. 26 is a memory, and the memory 26 inputs the ADDI signal from the microprocessor system 1 to be monitored onto the signal line 11, and further inputs the DATA1 signal onto the signal line 12.
This is for temporarily storing data according to the value on the signal line 42. Writing of the ADDi signal on the signal line 11 and the DATA signal on the signal line 12 is always performed while the microprocessor system 1 is operating normally. When a fault signal is output on the signal line 38 due to the occurrence of a fault, AND
The write signal on the signal line 42 is inhibited by the gate 27 from operating the microprocessor system 1, and the write operation is stopped. 25 is a write address designation counter (ADD 0NT) for the memory 26, which counts the data on the signal line 42 until the write operation is prohibited by the write inhibit signal on the signal @38. Specify a closing address for the address. Counter (ADDO)
NT) zs is just a binary counter, and after counting up to the address with the largest amount, it returns to specifying address O and repeats counting again. 28 is another microprocessor (OPU2), 29 is Ike's program memory (
ROMz).

The microprocessor 28 controls the entire program debugging device 2 according to the program stored in the program memory 29. 31 is an input/output interface. Microprocessor 28H input/output interface 3
When it learns that the information has been input to the signal line 38 through the I10 interface 31, it outputs the address designation from the first address to the last address to the memory 26, and sequentially reads the data inside the memory 26. It has a function of outputting the read data to a typewriter (TTY) 6. Reference numeral 30 denotes a temporary storage memory (RAM2) consisting of a random access memory, which is used as a work area for the microprocessor (OPU2) 2B.

The embodiment described above merely shows one implementation means of the microprocessor system debugging device, and the present device is not limited to the above embodiment. for example,
In this embodiment, only one limited address range is output as address range information, but in many cases it is necessary to set multiple address ranges, and in such cases, the comparison circuit outputs multiple address ranges. The configuration increases according to the range. In addition, in this first embodiment, the address range information is configured to be received sequentially from the device control side microprocessor, but for example, the address range information is received all at once when the power is turned on, and the address range information for the comparison circuit is set in the device. It may be performed by a microprocessor.

Furthermore, after the program driving history data has been recorded,
A method may be added in which a system reset is applied from the device side to the device control side microprocessor system for automatic recovery.

(Effects of the Invention) As explained above, the present invention constantly monitors the address information of the target microprocessor system, detects the abnormality when a program malfunction occurs, and records the program running history. By automatically performing these operations, there is an effect that program debugging can be performed effectively.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a microprocessor system debugging device according to the present invention.

Claims (1)

[Claims] a plurality of program modules for controlling the operation of an incorporated device by running inside or accessing a defined memory area; and a monitor program having an execution management function for the plurality of program modules. a microprocessor system debugging device connected to a microprocessor system incorporating a microprocessor system, the address range information indicating a running address range and an access address range of the program module, which is output before starting the program module; Address path information of the microprocessor system is input from the monitor program, and while the program module is running, the address path information is monitored so that the address path information deviates from the address range indicated by the address range information. When the trigger signal is generated, an address monitoring circuit for outputting a trigger signal and the address path information and data path information from the microprocessor system are always input and continuously stored, and when the trigger signal occurs, the address monitoring circuit outputs the trigger signal. a memory circuit for writing a predetermined amount of the address path information and the data path information from the memory circuit and stopping the operation after the writing is completed; The device is characterized in that it is configured to include a control circuit for reading the address path information and the data path information and outputting it to an output device, as well as monitoring the state of the address monitoring circuit and controlling the memory circuit. Microprocessor system debug equipment.