JPH08179812A - Programmable controller - Google Patents

Abstract

PURPOSE: To provide the programmable controller with which a user can easily recognize a factor when arithmetic delay is caused by problems of a user program. CONSTITUTION: A timer 5 for arithmetic delay monitor generates a timer output every time when scanning and timer count value are preset and time is up. When there is this timer output, a CPU 1 performs interruption processing, starts and executes an arithmetic delay monitor program previously stored in a ROM 2, writes the transfer of the current arithmetic execution address of the user program into the storage area of an arithmetic delay generation address set in a RAM 3 and sets an arithmetic error flag.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller.

[0002]

2. Description of the Related Art In a conventional programmable controller, when a calculation delay of a user program is detected, only its flag and error code are written in a memory section.

[0003]

However, it is difficult to find the cause of the operation delay due to the problem of the user program by only writing the flag and the error code as described above. The present invention has been made in view of the above problems, and an object of the present invention is to provide a programmable controller that allows a user to easily know the cause when an operation delay occurs due to a problem of a user program. is there.

[0004]

In order to achieve the above object, according to the invention of claim 1, a memory section including a CPU, a ROM, a RAM, an I / O interface, and an operation for monitoring an operation delay. In a programmable controller basically composed of a delay monitoring timer,
The time-up signal of the operation delay monitoring timer is input to the interrupt control port of the CPU. When the time is up, the CPU activates and executes the operation delay monitoring program by interrupt processing, and records the execution address of the user program when the interrupt occurs in the operation delay record. To be written in the memory section for use.

[0005]

According to the first aspect of the present invention, if the operation delay monitoring timer times out, the CPU activates and executes the operation delay monitoring program by interrupt processing, and automatically sets the execution address of the user program when the interrupt occurs. Since the data is written in the memory portion for the operation delay recording, the user program problem is caused by reading the address data written in the storage area of the operation delay occurrence address set in the RAM after the user knows the occurrence of the operation delay. Since the location can be easily known, it can be used as a reference when testing and debugging the user program, and a programmable controller that facilitates the development of the user program can be realized.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a basic configuration of a programmable controller according to an embodiment of the present invention. In the illustrated programmable controller, a CPU 1, a fixed program, a ROM 2 in which data is written, a user program, and a work are written. A memory unit including a RAM 3 used for securing an area or temporarily storing data, an I / O interface 4 for exchanging input / output data with an external device, and a calculation delay monitoring timer 5. The timer output of the operation delay monitoring timer 5 is connected to the interrupt port of the CPU 1.

FIG. 2 is a flow chart showing the basic operation of the programmable controller. After the power is turned on as shown in this flow chart, the CPU 1 first initializes based on the basic operation program stored in the ROM 2, and the initialization is performed. Is completed, the operation delay monitoring timer 5 is preset with a predetermined timer count value or a timer count value set by a peripheral tool (not shown) in the operation delay monitoring timer 5 in step (2-1). To start.

Then, in step (2-2), the state of a mode switch (not shown) provided in the programmable controller is judged, and if it is the programming mode (pROG), the program jumps to step (2-5). Performs peripheral tool service processing for setting and inputting various specifications. Run mode (R
If it is UN, I / I will be performed in steps (2-3) and (2-4).
After the O refresh and the calculation by the user program are executed, the peripheral tool service process of step (2-5) is executed.

Thereafter, the processes of steps (2-1) to (2-5) are repeated. That is, the calculation delay monitoring timer 5 is preset with a timer count value for each scan. The timer count value is set to a value that does not time up until the next preset at the normal calculation speed. Therefore, if the calculation of step (2-4) takes too long and the calculation is delayed, the calculation delay monitoring timer 5 times up and a timer output is generated. This timer output becomes an interrupt signal, and the CPU 1
Performs interrupt processing, and activates and executes a computation delay monitoring program stored in the ROM 2 in advance.

FIG. 3 shows a flow chart when this operation delay monitoring program is executed. The CPU 1 transfers the present operation execution address of the user program in step (3-1) and executes the operation set in the RAM 3. Write to the storage area of the delay occurrence address. Then, in the next step (3-2), the calculation error flag is set. After this, for example, a display, a display device or the like is used to display a calculation delay occurrence based on the calculation error flag to inform the user.

After knowing the occurrence of the operation delay, the user can easily know the problematic part of the user program by reading the address data written in the storage area of the operation delay occurrence address set in the RAM. . Therefore, it can be used as a reference when testing or debugging the user program, and facilitates the development of the user program.

[0012]

According to the first aspect of the present invention, if the operation delay monitoring timer times out, the CPU activates and executes the operation delay monitoring program by interrupt processing, and automatically sets the execution address of the user program when the interrupt occurs. Since the data is written in the memory portion for the operation delay recording, the user program problem is caused by reading the address data written in the storage area of the operation delay occurrence address set in the RAM after the user knows the occurrence of the operation delay. Since the location can be easily known, there is an effect that it can be used as a reference when testing or debugging the user program, and a programmable controller that facilitates the development of the user program can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing a basic operation of the above.

FIG. 3 is a flowchart showing an operation when a calculation delay occurs in the above.

[Explanation of symbols]

 1 CPU 2 ROM 3 RAM 4 I / O interface 5 Operation delay monitoring timer

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Claims (1)

[Claims] 1. A programmable controller basically comprising a CPU, a memory section including a ROM, a RAM, an I / O interface, and an operation delay monitoring timer for monitoring a delay in operation time. The time-up signal of the operation delay monitoring timer is input to the interrupt control port of the CPU, and when the time is up, the CPU starts and executes the operation delay monitoring program by interrupt processing.
A programmable controller characterized in that the execution address of a user program at the time of an interrupt is written in a memory section for computation delay recording.