JPS60220927A - Manufacturing device for semiconductor - Google Patents

Manufacturing device for semiconductor

Info

Publication number
JPS60220927A
JPS60220927A JP7792684A JP7792684A JPS60220927A JP S60220927 A JPS60220927 A JP S60220927A JP 7792684 A JP7792684 A JP 7792684A JP 7792684 A JP7792684 A JP 7792684A JP S60220927 A JPS60220927 A JP S60220927A
Authority
JP
Japan
Prior art keywords
container
electrode
reaction chamber
electrodes
lower electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7792684A
Other languages
Japanese (ja)
Inventor
Takashi Arita
有田 孝
Koshiro Mori
森 幸四郎
Michio Osawa
大沢 道夫
Zenichiro Ito
伊藤 善一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7792684A priority Critical patent/JPS60220927A/en
Publication of JPS60220927A publication Critical patent/JPS60220927A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium

Abstract

PURPOSE:To dispense with a shielding plate and to eliminate the power loss of turned- ON power by a method wherein, when mutually opposed two electrodes are provided in the interior of the reaction chamber container, wherein an amorphous thin film is grown on the surface of the substrate utilizing glow discharge, one of the two electrodes is formed on the base of the container as an electrode for power supply. CONSTITUTION:An upper electrode 9 provided with a heating heater 10 on its back surface and a lower electrode 11, which has been provided in opposition to the upper electrode 9 at a prescribed interval, are provided in the interior of a reaction chamber container 7, which has been earthed and has been sealed with O-rings 13. The electrode 11 is connected to a high-frequency power source RF, whose other end has been earthed, through a matching circuit. In this constitution, the lower electrode 11 is fitted in apertures bored in the base of the container 7 using terminal insulators 12 and the lower electrode 11 is integrally formed in one body with the base of the container 7. Moreover, a substrate 8 is adhered on the lower surface of the upper electrode 9. Raw gas is made to pass through apertures being provided on both sidewalls of the container 7 and a desired amorphous thin film is grown on the substrate 8. According to such a way, no discharge generates excluding the space between the opposed electrodes. As a result, a shielding plate and so forth can be dispensed with.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はグロー放電等を利用して、原料ガスを分解し、
基板上に非晶質薄膜を堆積させる半導体の製造装置に関
するものである。
[Detailed description of the invention] Industrial application field The present invention decomposes raw material gas using glow discharge etc.
The present invention relates to a semiconductor manufacturing apparatus that deposits an amorphous thin film on a substrate.

従来例の構成とその問題点 近年、非晶質シリコン太陽電池に代表されるように、非
晶質半導体の産業界への進出は目ざましく、その製造装
置についても、いろいろな新型装置の開発が進められて
いる。以下、図面を参照しながら従来の半導体の製造装
置について説明を行第1図は従来のグロー放電を利用し
た半導体製造装置の反応室の概略図である。第1図にお
いて、1は反応室容器、2は容器1内に設けた下部電極
で整合回路を経て13..66 Ml−1z の高周波
電源RFに接続されている。3は下部電極2と一定の間
隙を保持してアース電位に保たれたシールド板、4は基
板、5は上部電極、6は上記基板を加熱するだめの加熱
ヒータである。以上のように構成された半導体の製造装
置において、以下その動作について説明する。原料ガス
、例えばH2ガスで10%に希釈されたS IHaガス
を矢印のように反応ガス入口より反応室容器1内に導入
し、排気処理することで一定の真空度に保持する。上部
電極5に取りつけられた基板4は、加熱ヒータ6により
適温に保持される。次に下部電極2に高周波電源RFよ
り整合回路を経て電力を供給すると、両電極2゜6間に
グロー放電が発生する。このグロー放電により発生した
S I H4のプラズマ中に存在する分解生成分S I
H2,S iH、S i 、Hなどのラジカル種が、基
板表面上へ到達し、表面反応により基板上に非晶質シリ
コン薄膜を堆積することができる。しかし7ながら上記
のような構成の半導体の製造装置では、第1図に示した
ように、下部電極2と反応室容器1の内壁との間で生じ
る放電を防ぐために、アース電位に保たれたシールド板
3を、下部電極と一定の間隙を保持して付設する必要が
あった。
Conventional configurations and their problems In recent years, amorphous semiconductors, as typified by amorphous silicon solar cells, have entered the industrial world at a remarkable pace, and various new types of manufacturing equipment have been developed. It is progressing. A conventional semiconductor manufacturing apparatus will be described below with reference to the drawings, and FIG. 1 is a schematic diagram of a reaction chamber of a conventional semiconductor manufacturing apparatus using glow discharge. In FIG. 1, 1 is a reaction chamber container, 2 is a lower electrode provided in the container 1, and 13. .. It is connected to a high frequency power supply RF of 66 Ml-1z. Reference numeral 3 designates a shield plate which is kept at ground potential by maintaining a constant gap from the lower electrode 2, 4 a substrate, 5 an upper electrode, and 6 a heater for heating the substrate. The operation of the semiconductor manufacturing apparatus configured as described above will be described below. A raw material gas, for example, SIHa gas diluted to 10% with H2 gas, is introduced into the reaction chamber container 1 from the reaction gas inlet as shown by the arrow, and maintained at a constant degree of vacuum by evacuation treatment. The substrate 4 attached to the upper electrode 5 is maintained at an appropriate temperature by a heater 6. Next, when power is supplied to the lower electrode 2 from the high frequency power source RF via a matching circuit, a glow discharge is generated between both electrodes 2.6. The decomposition products S I present in the S I H4 plasma generated by this glow discharge
Radical species such as H2, S iH, S i , H, etc. can reach the substrate surface and deposit an amorphous silicon thin film on the substrate by surface reaction. However, in the semiconductor manufacturing equipment with the above configuration, as shown in FIG. It was necessary to attach the shield plate 3 while maintaining a certain gap from the lower electrode.

それに加えて、シールド板3と下部電極2との間で強い
異常放電が生じ、投入パワーのロスや、イオン衝撃によ
る堆積膜のピンホール発生等の原因になっていた。また
下部電極2の下になる反応室容器1の内底部に堆積した
粉状の堆積物を除去し、管内を掃除する時にも下部電極
2が邪摩になってこの下部電極を取りはずさなければな
らず、手間取るという問題があった。
In addition, a strong abnormal discharge occurs between the shield plate 3 and the lower electrode 2, causing loss of input power and generation of pinholes in the deposited film due to ion bombardment. Furthermore, when removing powdery deposits that have accumulated on the inner bottom of the reaction chamber vessel 1 below the lower electrode 2 and cleaning the inside of the tube, the lower electrode 2 becomes a nuisance and must be removed. However, there was a problem in that it was time-consuming.

発明の目的 本発明は上記欠点に鑑み、下部電極にシールド板を必要
とせず、なおかつ、上下電極間以外の放電による投入パ
ワーのロスをなくし、良質の膜が堆積できる半導体の製
造装置を提供するものであり、また反応室の掃除も容易
に行うことのできる構造としたことを目的とする。
Purpose of the Invention In view of the above drawbacks, the present invention provides a semiconductor manufacturing apparatus that does not require a shield plate for the lower electrode, eliminates input power loss due to discharge other than between the upper and lower electrodes, and can deposit a high-quality film. The purpose of the present invention is to provide a structure that allows easy cleaning of the reaction chamber.

発明の構成 この目的を達成するために、本発明の半導体の製造装置
は、少なくとも一対の電極を有する反応室容器において
、上記一対の電極のうち電力が供給される一方の電極が
上記反応室容器の一部分を形成するように構成したこと
を特徴とするものである。
Structure of the Invention To achieve this object, the semiconductor manufacturing apparatus of the present invention provides a reaction chamber container having at least one pair of electrodes, in which one of the pair of electrodes to which electric power is supplied is connected to the reaction chamber container. It is characterized by being configured so as to form a part of the.

実施例の説明 以下本発明の一実施例について、図面を参照しながら説
明する。第2図は本発明の一実施例における半導体の製
造装置の概略図を示すものである。
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows a schematic diagram of a semiconductor manufacturing apparatus according to an embodiment of the present invention.

第2図において、7は反応室容器、8は基板、9は上部
電極、1oは加熱ヒータ、13は○リングであり、これ
らは第1図の構成と同じものである。
In FIG. 2, 7 is a reaction chamber container, 8 is a substrate, 9 is an upper electrode, 1o is a heater, and 13 is a ring, which are the same as those in FIG. 1.

11は反応室容器7の底部の一部分を兼ねた下部電極で
、アース電位に保たれた反応室容器7とは絶縁物12に
より電気的に絶縁されておシ、整合回路を経て高周波電
源RFに接続されている。以上のような構成にすること
によりシールド板を設けなくても反応室内部では、9,
11の上下の両電極間以外では放電しないし、反応室外
部では、大気圧雰囲気であるので、下部電極の裏面に金
属物体を近づけたい限り放電はしない。従って投入パワ
ーのロスを防ぐことができ、異常放電によるピンホール
の発生のない良質の堆積膜を得ることができた。また反
応室7内部もこれ徒での下部電極のような突起物がなく
なるので、従来例のように下部電極を取りはずして粉状
反応生成物を除去することも不要となり、非常に楽に保
守点検や清掃を行うことができた。
Reference numeral 11 denotes a lower electrode that also serves as a part of the bottom of the reaction chamber container 7. It is electrically insulated from the reaction chamber container 7, which is kept at ground potential, by an insulator 12, and is connected to a high frequency power source RF through a matching circuit. It is connected. With the above configuration, 9,
No discharge occurs except between the upper and lower electrodes 11, and since the atmosphere outside the reaction chamber is atmospheric pressure, no discharge occurs unless a metal object is brought close to the back surface of the lower electrode. Therefore, it was possible to prevent loss of input power and obtain a deposited film of good quality without pinholes caused by abnormal discharge. In addition, since there is no longer a protrusion like a lower electrode inside the reaction chamber 7, it is no longer necessary to remove the lower electrode and remove powdery reaction products as in the conventional case, making maintenance and inspection very easy. I was able to do some cleaning.

発明の効果 以上のように本発明は、少なくとも一対の電極をもつ、
非晶質薄膜を堆積させる反応室容器において、上記一対
の電極のうち電力が供給される一方の電極が上記反応室
容器の一部分を形成するように構成したことにより、下
部電極にシールド板を必要とせず、なおかつ、上下電極
間以外の放電による投入パワーのロスをなくして良質の
堆積膜を製造することができ、また反応室の掃除も容易
に行うことができるようになった。
Effects of the Invention As described above, the present invention has at least one pair of electrodes.
In the reaction chamber vessel in which the amorphous thin film is deposited, one of the pair of electrodes to which power is supplied forms a part of the reaction chamber vessel, so that a shield plate is not required for the lower electrode. In addition, it is possible to produce a high quality deposited film by eliminating input power loss due to discharge other than between the upper and lower electrodes, and it has become possible to easily clean the reaction chamber.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体の製造装置の反応室の概略図、第
2図は本発明の実施例における半導体の製造装置の反応
室の概略図である。 1.7 ・・・・反応室容器、5,9・−一上部電極、
2.11・・−・下部電極、12−・絶縁物。
FIG. 1 is a schematic diagram of a reaction chamber of a conventional semiconductor manufacturing apparatus, and FIG. 2 is a schematic diagram of a reaction chamber of a semiconductor manufacturing apparatus in an embodiment of the present invention. 1.7...Reaction chamber container, 5,9...-first upper electrode,
2.11...lower electrode, 12--insulator.

Claims (1)

【特許請求の範囲】[Claims] 内部に少なくとも一対の電極をもつ、非晶質薄膜を堆積
させる反応室容器を備え、前記一対の電極のうち電力が
供給される一方の電極が前記反応室容器の一部分を形成
したことを特徴とする半導体の製造装置。
A reaction chamber for depositing an amorphous thin film having at least a pair of electrodes therein, and one of the pair of electrodes to which electric power is supplied forms a part of the reaction chamber. Semiconductor manufacturing equipment.
JP7792684A 1984-04-18 1984-04-18 Manufacturing device for semiconductor Pending JPS60220927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7792684A JPS60220927A (en) 1984-04-18 1984-04-18 Manufacturing device for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7792684A JPS60220927A (en) 1984-04-18 1984-04-18 Manufacturing device for semiconductor

Publications (1)

Publication Number Publication Date
JPS60220927A true JPS60220927A (en) 1985-11-05

Family

ID=13647690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7792684A Pending JPS60220927A (en) 1984-04-18 1984-04-18 Manufacturing device for semiconductor

Country Status (1)

Country Link
JP (1) JPS60220927A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0538868U (en) * 1991-10-29 1993-05-25 三洋電機株式会社 Semiconductor thin film forming equipment
JPH0541135U (en) * 1991-11-01 1993-06-01 三洋電機株式会社 Semiconductor thin film forming equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0538868U (en) * 1991-10-29 1993-05-25 三洋電機株式会社 Semiconductor thin film forming equipment
JPH0541135U (en) * 1991-11-01 1993-06-01 三洋電機株式会社 Semiconductor thin film forming equipment

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