JPS60220871A - Detecting device for phase difference - Google Patents

Abstract

PURPOSE:To detect the phase difference of an optional frequency with the precision of the pulse width of a clock by controlling the number of input clocks to a counter according to the phase difference of a zero-cross detection output. CONSTITUTION:The 1st and 2nd zero-cross detecting circuits 1A and 1B detect the point where an input voltage changes from minus to plus and an FF2 is set and reset with respective detection pulses and sends a pulse with width corresponding to the phase difference between detection pulses; when this pulse is inputted to a counter 4, the number of clocks (g) is counted by the width of the phase difference. The count output is held in a register 5 at the rise of the output signal of a delay circuit 6 and its output is applied with D/A-conversion 7 and sent out.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for detecting a phase difference between two signals in periodically repeating waveforms.

FIG. 1 is a block diagram of a conventional phase difference detection device of this type. In the figure, (IA) and (IB) are the first and second zero cross detection circuits that detect the point where the input voltage changes from negative to positive and generate a pulse, and (2) are the set input and reset A flip signal that generates a
The flop (31 is an integrating circuit that integrates and smoothes the entire input signal.) A conventional phase difference detection device is constructed as described above.

The sine wave a of the first frequency is transmitted to the first zero cross detection circuit (
When input to IA), the pulse waveform C at the time of input is output, input to the input terminal of the flip group (21 cellar), and input to the flip flop (21 output e
becomes a logical 1 state. Next, when the sine wave of the second frequency is input to the second zero-cross detection circuit (IB),
The pulse waveform d at that point is output.

The output of the flip-flop (21) is input to the reset input terminal of the flip-flop (21), and the output of the flip-flop (21) is logic 0.
It is in a state of The output signal e of this flip-flop (2) is input to the integrating circuit (31), and a smoothed signal f is outputted.The time chart thereof is shown in FIG.

However, in the above-mentioned 1 phase difference detection device, since the output of the flip-flop +21 is smoothed by an integrating circuit and output, even if the phase difference of the input signal is the same, it varies depending on one frequency. There was a drawback that the relationship with the output of the detection device had to be converted.

This invention was made with the aim of improving this drawback.In order to detect the phase difference, the number of clocks input to the counter is controlled by a fully-solid flop and a delay circuit, and the number of clocks input manually is held in a register. Especially,
Any frequency.

This paper proposes a device that can output a value proportional to the phase difference.

FIG. 3 is a block diagram showing an embodiment of the present invention,
CIA) and (IB) are first and second zero-cross detection circuits that detect when the input voltage changes from negative to positive and generate pulses, and (2) generates pulses by set input and reset input. (4) is a resistor that holds input data; (5) is a delay circuit that delays the signal in synchronization with the clock signal.

(6) is a D/A that converts digital signals to analog signals.
It is a converter.

The operation of this invention will be explained. In FIG. 3, the operations of the first and second zero-cross detection circuits (IA) 1 (IB) and the flip-flop (2) are the same as those explained in FIG. A pulse e having a width equal to the phase difference is output. When this signal e is input, the number of clocks of the clock signal f is counted by the width of the two phase difference, and the output of the counter (4) increases and stops. Then, the output signal is held in the register (5) at the rising edge of the output signal i of the delay circuit (61).
The count number at that time is output as the output signal j. Therefore, the output signal j of the register (5) is converted into an analog signal kK by a D/A converter (71) and output.In preparation for the next detection, the counter (4) outputs the output signal of the delay circuit (6). The output of the counter is reset to 0 by the rising edge of 1.

FIG. 4 shows a time chart of this embodiment.

As explained above, according to the present invention, the phase difference between various frequencies can be detected with the precision of the pulse width of the clock signal.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional phase difference detection device, Figure 2 is a block diagram showing a conventional phase difference detection device.
The figure is a diagram showing the time chart of FIG. 1. FIG. 3 is a block diagram showing an embodiment of the present invention. FIG. 4 is a diagram showing the time chart of FIG. 3. In the figure, (IA) and (IB) are the first and second zero cross detection circuits, (2) is a flip-flop, and (31
is an integration circuit, (41 is a counter, (5) is a register, (
6) is a delay circuit that delays in synchronization with the clock, and (7) is a D/A converter. Identical or corresponding parts in FIGS. 9 and 9 are designated by the same reference numerals. Agent Masuo Oiwa Figure 1 Figure 2 Figure 4

Claims (1)

[Claims] A first zero cross detection circuit receives a reference signal and generates a pulse when the reference signal changes from negative to positive, and a second zero cross detection circuit receives all input signals and generates a pulse when the signal changes from negative to positive. The output of the first zero-cross detection circuit is input to the first input terminal of the zero-cross detection circuit, and the output of the second zero-cross detection circuit is input to the second input terminal. A flip-flop, a delay circuit that inputs the output signal of the second zero-cross detection circuit and outputs a delayed output signal, and the output of the flip-flop is connected to a first input terminal of the three input terminals. , a counter to which a reference clock signal is input to the second input terminal, the output of the delay circuit is input to the third input terminal, and the output of the above counter is input to the first input terminal of the two input terminals. is,
The second input terminal is provided with an output of the delay circuit, a register for holding data, and a D/A converter for inputting the output of the register and converting it into an analog signal. Phase difference detection device.