JPS60220614A - Device for changing smoothly digital quantity - Google Patents

Device for changing smoothly digital quantity

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Publication number
JPS60220614A
JPS60220614A JP7698284A JP7698284A JPS60220614A JP S60220614 A JPS60220614 A JP S60220614A JP 7698284 A JP7698284 A JP 7698284A JP 7698284 A JP7698284 A JP 7698284A JP S60220614 A JPS60220614 A JP S60220614A
Authority
JP
Japan
Prior art keywords
output
adder
input
latch
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7698284A
Other languages
Japanese (ja)
Inventor
Atsushi Ito
厚 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7698284A priority Critical patent/JPS60220614A/en
Publication of JPS60220614A publication Critical patent/JPS60220614A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To eliminate influences of a converter which obtains a reciprocal of a variation, by providing a latch circuit, where the output of an adder is held temporarily, and the adder, which outputs a carry output, instead of the converter and a frequency divider. CONSTITUTION:When a variation (c) is set to a register 2 from a computer 1, an adder 7 adds an absolute volue (d) of the variation and the output of a latch 8. The latch 8 holds an output (j) of the adder 7 and updates data by a clock (g). When the value of the adder 7 exceeds the maximum value, the adder 7 outputs a carry output (h) to carry. Then, an up/down counter 6 outputs a smoothly changed digital quantity by an initial value (a), a change direction (b) after setting, and the carry output (h). Thus, influences of the converter which obtains a reciprocal of the variation are eliminated.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明はディジタル量をなめらかに変化させる装置に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an apparatus for smoothly changing a digital quantity.

〔従来技術〕[Prior art]

従来のこの種装置のブロックを第1図に示す。 A block diagram of a conventional device of this type is shown in FIG.

図において(、)は入力される初期値信号、 (c)V
1入力される変化量信号、(f)は人力されるリセット
信号である。
In the figure, (,) is the input initial value signal, (c) V
1 is an input change amount signal, and (f) is a manually inputted reset signal.

(1)はディジタル信号の演算、記憶を行ない上記初期
値信号、変化量信号、およびリセット信号を出力する計
算機、(2)は上記計算機(1)のディジタル信号を保
持しておくレジスタ、(3)はディジタル入力信号を逆
数に比例した値に変換する変換器、(5)はクロックを
入力値(D)で分局する分局器、(6)はアップダウン
切替え入力端の、初期値入力端り。
(1) is a computer that calculates and stores digital signals and outputs the initial value signal, variation signal, and reset signal; (2) is a register that holds the digital signals of the computer (1); (3) ) is a converter that converts the digital input signal into a value proportional to the reciprocal, (5) is a divider that divides the clock by the input value (D), and (6) is the initial value input terminal of the up/down switching input terminal. .

クロック入力端Tを有し2分局器(5)の出力によりア
ップ・カウントまたはダウン・カウントを行うアップ/
ダウン・カウンタである。
An up/down counter that has a clock input terminal T and performs up-counting or down-counting based on the output of the 2-way divider (5).
It is a down counter.

従来のこの種装置は上記のように構成され、レジスタ(
2)に計算機(1)から変化量(c)が設定されると変
換器(31Kよシ変化量(c)の逆数に比例した値(e
)がえられる2分局器(5)はクロック(g)を変換器
の出力(e)で分周する2分周器(5)はレジスタ(2
)にデータを入力したときリセット(f)によ゛り初期
状態にされる。
A conventional device of this type is configured as described above, and has a register (
2) When the amount of change (c) is set from the calculator (1), the converter (31K) sets a value (e) proportional to the reciprocal of the amount of change (c).
) is obtained by dividing the clock (g) by the output (e) of the converter.
) is set to the initial state by reset (f).

この初期状態から分局器(5)は分局を開始する1分周
器(5)の出力信号(h)の周波数は発振器(4)の周
波数を変換器(3)の出力(e)で分周するため変化量
(c)に比例した値となる。
The frequency of the output signal (h) of the divider (5) is determined by dividing the frequency of the oscillator (4) by the output (e) of the converter (3). Therefore, the value is proportional to the amount of change (c).

=(gの周辣数)×(変化量:c)Xmn:変換器の定
数 gの周波数は一定 アップ/ダウン・カウンタ(6)は計算機(1)から初
期値(a)を設定径変化量(c)の符号である変化方向
(b)により増加又は減少の方向がきまる。またアップ
/ダウン・カウンタは初期値設定径前記信号(h)によ
り初期値から指定した変化量に相当する速度で1ビット
づつ変化するディジタル量を出力する。
= (number of cycles of g) x (amount of change: c) The direction of increase or decrease is determined by the change direction (b), which is the sign of (c). In addition, the up/down counter outputs a digital amount that changes bit by bit at a speed corresponding to the amount of change designated from the initial value by the initial value setting diameter signal (h).

しかるに上記のように変換器(3)により変化量の逆数
を計算するため変化量”O”の設定が不可能であり出力
信号(1)を止めておくことができないという欠点があ
った。
However, as described above, since the reciprocal of the amount of change is calculated by the converter (3), it is impossible to set the amount of change "O" and there is a drawback that the output signal (1) cannot be stopped.

変換器(3)のために変化量と同一の分解能を得るため
には変化量のビット幅をnとすると変換器(3)の出力
(e)のビット幅は2nとなシロビットの分解能をえる
ために2nビツトの変換器と分局器が必要であるという
欠点があった。
In order to obtain the same resolution as the amount of change for the converter (3), if the bit width of the amount of change is n, the bit width of the output (e) of the converter (3) is 2n to obtain a resolution of silobits. The disadvantage is that a 2n-bit converter and a branching unit are required for this purpose.

変化量設定後分局器(5)を初期化する必要があるため
直前の分局器の内容が初期化されてしまい設定後は新た
に分周を始めなければならないという欠点があった。
Since it is necessary to initialize the divider (5) after setting the amount of change, the contents of the previous divider are initialized, and there is a drawback that frequency division must be started anew after the setting.

〔発明の実施例〕[Embodiments of the invention]

この発明はこのような問題点の改善を図ったもので、以
下図に示す実施例を説明する。
The present invention aims to improve such problems, and an embodiment shown in the drawings will be described below.

第2図はこの発明の一実施例を示す図であり。FIG. 2 is a diagram showing an embodiment of the present invention.

+11 +2)(61は上記した従来の装置と同一のも
のである。
+11 +2) (61 is the same as the conventional device described above.

(7)は入力A、Bの2つの信号を加算する加算器。(7) is an adder that adds two input signals, A and B.

(8)は加算器(7)の出力を一時保持し出力が加算器
(7)の一方の入力に接続されるラッチである。
(8) is a latch which temporarily holds the output of the adder (7) and whose output is connected to one input of the adder (7).

上記のように構成されたこの発明の装置において、レジ
スタ(2)に計算機(1)から変化量(c)が設定され
ると加算器(7)は変化量の絶対値(d)とラッチ(8
)の出力を加算する。ラッチ(8)は前記加算器の出力
(j)を保持しクロック(g)によシデータを更新する
In the device of the present invention configured as described above, when the amount of change (c) is set in the register (2) from the computer (1), the adder (7) adds the absolute value (d) of the amount of change and the latch ( 8
). The latch (8) holds the output (j) of the adder and updates the data using the clock (g).

このように時刻Tに加算器(7)はレジスタ(2)の変
化量と時刻T−1の加算器出力を保持するラッチ(8)
の出力を加算する。加算器(7)の出力は発振器(4)
のクロックごとに変化量を加算していく2時刻が温み加
算器の値が加算器の最大値をこえると加算器は桁上げ出
力(h)を出力して加算器は桁上げをおこす。
In this way, at time T, the adder (7) is connected to the latch (8) that holds the amount of change in the register (2) and the adder output at time T-1.
Add the outputs of . The output of the adder (7) is the oscillator (4)
When the value of the warmth adder exceeds the maximum value of the adder at two times when the amount of change is added every clock, the adder outputs a carry output (h) and the adder performs a carry.

ここで桁上げ出力(h)の周波数は次のようになる。Here, the frequency of the carry output (h) is as follows.

(hの周波数)=(発振器の周波数)×(変化t)÷(
加算器の最大値) ここで発振器の周波数と加算器の最大値は一′定のため
桁上げ出力(h)の周波数は変化量に比例する。
(frequency of h) = (frequency of oscillator) × (change t) ÷ (
Maximum value of the adder) Here, since the frequency of the oscillator and the maximum value of the adder are constant, the frequency of the carry output (h) is proportional to the amount of change.

アップ/ダウン・カウンタ(6)は従来の回路と同様に
初期値(3)を設定径変化方向(b)と上記桁上げ出力
(h)によシ計算機(1)より設定された変化量で1ビ
ツトづつなめらかに変化したディジタル量を出力すると
とができる。
As with the conventional circuit, the up/down counter (6) changes the initial value (3) by the amount of change set by the computer (1) based on the set radius change direction (b) and the carry output (h). It is possible to output a digital quantity that changes smoothly bit by bit.

なお上記実施例では本装置を計算機により制御している
がスイッチ等によシ手動設定で行なっても同様の動作を
期待することができる。
In the above embodiment, the present device is controlled by a computer, but the same operation can be expected even if the device is manually set using a switch or the like.

〔発明の効果〕 以上説明したようにこの発明によれば変換器の逆数をめ
る変換器の併置のない外挿装置を作ることができ、実現
する装置も単純で小型化できる利点がある。
[Effects of the Invention] As explained above, according to the present invention, it is possible to create an extrapolation device without co-locating a converter for calculating the reciprocal of a converter, and there is an advantage that the device to be realized can be simple and miniaturized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来におけるディジタル量をなめらかに変化さ
せる装置を示すブロック図、第2図はこの発明の一実施
例を示すブロック図、第3図は第2図における実施例の
主要部分のタイムチャートを示す図である。 図において(1)は計算機、 (21Viレジスタ、 
+31Vi変換器、(4)は発振器、(5)は分局器、
(6)はアップ/ダウン・カウンタ、(7)は加算器、
(8)はラッチである。 なお2図中同一符号は同一まだは相当部分を示す。 代理人大岩増雄
Fig. 1 is a block diagram showing a conventional device for smoothly changing a digital amount, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a time chart of the main parts of the embodiment in Fig. 2. FIG. In the figure, (1) is a computer, (21Vi register,
+31Vi converter, (4) is oscillator, (5) is branching unit,
(6) is an up/down counter, (7) is an adder,
(8) is a latch. Note that the same reference numerals in the two figures indicate the same or corresponding parts. Agent Masuo Oiwa

Claims (1)

【特許請求の範囲】[Claims] レジスタと、ラッチと、加算器と、アップ/ダウン・カ
ウンタとから構成されディジタル量をなめらかに変化さ
せる装置において、変化量データを入力し一時保持する
レジスタと、前記加算器の出力信号を入力し一時保持す
るラッチと、2つの入力端子のうちの第一の入力端に上
記レジスタの出力を入力し、第2の入力端に上記ラッチ
の出力を入力し、加算出力と桁上げ出力を出力する加算
器と、3つの入力端のうち第1の入力端に初期値データ
を入力し、第2の入力端に上記加算器の桁上げ出力を入
力し、第3の入力端には上記レジスタの出力を入力し、
増加又は減少を行うアップ/ダウン・カウンタを備えた
ことを特徴とするディジタル量をなめらかに変化させる
装置。
In a device that smoothly changes a digital amount, which is composed of a register, a latch, an adder, and an up/down counter, a register that inputs and temporarily holds change amount data and an output signal of the adder are input. Input the output of the above register into the latch for temporary holding and the first input terminal of the two input terminals, input the output of the above latch into the second input terminal, and output the addition output and carry output. Initial value data is input to the first input terminal of the adder and three input terminals, the carry output of the adder is input to the second input terminal, and the data of the above register is input to the third input terminal. Enter the output and
A device for smoothly changing a digital quantity, characterized by comprising an up/down counter that increases or decreases.
JP7698284A 1984-04-17 1984-04-17 Device for changing smoothly digital quantity Pending JPS60220614A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7698284A JPS60220614A (en) 1984-04-17 1984-04-17 Device for changing smoothly digital quantity

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7698284A JPS60220614A (en) 1984-04-17 1984-04-17 Device for changing smoothly digital quantity

Publications (1)

Publication Number Publication Date
JPS60220614A true JPS60220614A (en) 1985-11-05

Family

ID=13620981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7698284A Pending JPS60220614A (en) 1984-04-17 1984-04-17 Device for changing smoothly digital quantity

Country Status (1)

Country Link
JP (1) JPS60220614A (en)

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