JPS60220423A - Processing system of flml instruction - Google Patents

Abstract

PURPOSE:To process in a short time the original data variable in length on a memory by applying an FLML (find left most one long) instruction to the original data. CONSTITUTION:For the original data DT of variable length stored in a memory MEM, the data on the store address and the address designated by the range length to be decided are transferred to deciding registers r1-r4 to decide ''1'' and ''0'' successively from the left bits. At the same time, the contents are renewed to the prescribed value to count the ''0'' deciding frequency when ''0'' is decided. Then the store addresses are renewed successively when the contents of registers r1-r4 are all equal to ''0''. Then the corresponding data DT is stored to registers r1-r4, and the position of bit ''1'' at the most left side is obtained when bit ''1'' is decided.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an FLML instruction processing method that can detect a bit "1" position by an FLML instruction in a short time in original data of many bits.

(2) Conventional technology and problems In large general-purpose computers, the original data is
It may be necessary to perform processing to determine whether a bit is "1" or "0" and to position the bit that was initially determined to be "1". The command that performs this process is called the FLM command.5゜FLM is Find Lef
It is an abbreviation of tMo5tOne. In conventional FLM processing, original data is stored in a general-purpose register that stores 32 bits (4 bytes), and the contents of the register are "1" and "0."
”, and in this process, only fixed 32-bit original data was handled. Therefore, now that the original data to be processed is often 32 bits or more, it is now possible to use a single instruction. It is necessary to repeat the processing for every 32 bits, which wastes the processing time of repeatedly storing and resetting data. Also, as processing by the FLM instruction, special calculations are required to locate the bit that is initially determined to be "1". It was necessary to set up a process for this purpose.

(3) Object of the Invention An object of the present invention is to improve the above-mentioned drawbacks and to provide a data processing method that can process variable-length original data on a storage device in a short time by applying FLML instructions. FL
What is ML?Fin6Laf't Moat One Lo
It is an abbreviation of ng.

(4) Structure of the Invention The structure of the present invention to achieve the above-mentioned object is to store data at an address specified by a range length to be determined as a storage address by using a variable-length original data stored in a storage device. is transferred to the judgment register, and the bits on the left side are sequentially judged as ``1'' and ``0'', and at the same time, in the case of 4 bits, the contents are updated to a predetermined value, and a register is provided to count the number of times ``0'' is judged. , when the contents of the judgment register are all “0”, the storage address is updated sequentially and the original data of the corresponding storage device is stored in the judgment register, and when the bit “1” is judged, the register that counts the number of judgments is The purpose is to locate the leftmost bit "1" based on the count value.

(5) Embodiment of the invention FIG. 1 shows the components of an embodiment of the invention. MEM is a storage device in which original data is stored, CPU is a central processing unit, DT is original data, and FLP is FLML. Instruction execution unit, R1 to Rn are general-purpose registers, r 1 * r 2 g
. . . rn is a register of the FLML instruction execution unit, and TL is a data transmission path. Now central processing unit CPU iC F
If the LML command is given in the form FLML RI R2D (R3), then the FLML command execution part FL
P operates as follows.

Add an offset value to the address indicated by (-(1 (13)) and set the value in address register r2.

(1) Set the length of the original data indicated by R2 in the range register (r5).

(c) Set the counter register (r4) to zero.

) Transfer one byte of the contents of the storage device indicated by the address register (rl) to the bit search register (rl).

(e) Determine whether the bit is "D" or "1" sequentially from the left side of the bit investigation register (rl).

(to) If the bit is "0", the counter register (r4) is incremented by "1" and bit determination is continued.

(g) When the investigation of all data (8 hits) in the bit investigation register (rl) is completed, the address register (12)
is incremented by "1" and the range register (r3) is subtracted by "1". At this time, if the range register (r3) is set to "o", then the range register (r3) returns to rOJ.
In this case, the condition code Cc is set to a value Ca="0" indicating that all bits investigated are "0", and the process is terminated.

(g) When the bit in the investigation register (rl) is “1”, the value of the counter register (r4) is transferred to the register R1, and the condition code CC is “1”.
” and the process ends.

The above operation is shown in FIG. 2 using a 7'c1-chart. As seen in this process, multiple bits of original data can be processed with a single FLML instruction. Conventionally, the bit length that could be processed by a single instruction was limited.

(6) Effect of the invention In this way, according to the present invention, even if the data is long,
Investigations can be conducted in a shorter time. For example, by applying FLML commands, you can improve system performance by checking whether the real space in units of pages has been allocated to logical space, whether the logically divided space on the disk is in use, etc. You can make improvements.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of the present invention, and FIG. 2 shows an operation flowchart of FIG. 1. MgM...Storage device DT...Original data CPU...
・Central processing unit FLP...FLML instruction execution unit R1
~Rn...General-purpose register r 1 g r2 e "" rH=・FLM instruction execution°
Row section register TL --- Data transmission line CC --- Condition code Patent applicant: Fujitsu Limited (and one other person) Agent: Sosuke Tsuchi Suzuki, patent attorney Figure 1

Claims (1)

[Claims] Regarding the variable length original data stored in the storage device,
The data at the address specified by the storage address and the range length to be determined is transferred to the determination register, and the pressure is determined sequentially from the left bit as "1" or "0#", and at the same time, if it is 90", the content is set to a predetermined value. A register is provided to update and count the number of “0” judgments, and the contents of the judgment register are all “0”.
An FLML instruction processing method characterized in that when , the storage address is sequentially updated and the position of the leftmost bit "1" is set based on the count value of the corresponding register.