JPS6285372A - Comparing and swapping system in multi-processor system - Google Patents

Comparing and swapping system in multi-processor system

Info

Publication number
JPS6285372A
JPS6285372A JP22611585A JP22611585A JPS6285372A JP S6285372 A JPS6285372 A JP S6285372A JP 22611585 A JP22611585 A JP 22611585A JP 22611585 A JP22611585 A JP 22611585A JP S6285372 A JPS6285372 A JP S6285372A
Authority
JP
Japan
Prior art keywords
signal line
comparing
write
address
write data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22611585A
Other languages
Japanese (ja)
Inventor
Susumu Shibazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22611585A priority Critical patent/JPS6285372A/en
Publication of JPS6285372A publication Critical patent/JPS6285372A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To execute exclusive control by a comparing and swapping system,by controlling whether a rewriting processing of data which has been stored in a prescribed area can be executed or not, in accordance with a result of comparison of a comparing means.
CONSTITUTION: A processor 1 which is not shown in the figure stores an address of a counting type semaphore in an address holding means 27 through a signal line 121, and also stores write data in a write data holding means 26 through a signal line 122. A decoding means 20 sends out a write instruction through a signal line 201 to a common storage device 5 which is not shown in the figure, and also sends out a write address through a signal line 252, and the write data through a signal line 253 from the means 27 and the means 26, respectively. As for the write instruction of the signal line 201, AND is taken with a result of comparison of the means 25 on a signal line 251 in an AND circuit 28, and a logical signal is sent out to a signal line 281. Accordingly, only when an output of the means 25 is '1', rewriting of the counting type semaphore of the device 5 is executed.
COPYRIGHT: (C)1987,JPO&Japio
JP22611585A 1985-10-09 1985-10-09 Comparing and swapping system in multi-processor system Pending JPS6285372A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22611585A JPS6285372A (en) 1985-10-09 1985-10-09 Comparing and swapping system in multi-processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22611585A JPS6285372A (en) 1985-10-09 1985-10-09 Comparing and swapping system in multi-processor system

Publications (1)

Publication Number Publication Date
JPS6285372A true JPS6285372A (en) 1987-04-18

Family

ID=16840067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22611585A Pending JPS6285372A (en) 1985-10-09 1985-10-09 Comparing and swapping system in multi-processor system

Country Status (1)

Country Link
JP (1) JPS6285372A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06301657A (en) * 1993-02-22 1994-10-28 Internatl Business Mach Corp <Ibm> Method for parallel management
JP2009134771A (en) * 2005-12-01 2009-06-18 Sony Computer Entertainment Inc Technology for implementing atomic compare and swap instruction using specific processor
US7940706B2 (en) 2001-10-01 2011-05-10 International Business Machines Corporation Controlling the state of duplexing of coupling facility structures
JP2012531682A (en) * 2009-12-22 2012-12-10 インテル・コーポレーション SIMD vector synchronization
JP2020506483A (en) * 2017-02-08 2020-02-27 エイアールエム リミテッド Compare and swap transaction

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06301657A (en) * 1993-02-22 1994-10-28 Internatl Business Mach Corp <Ibm> Method for parallel management
US9253046B2 (en) 1998-09-10 2016-02-02 International Business Machines Corporation Controlling the state of duplexing of coupling facility structures
US9565013B2 (en) 1998-09-10 2017-02-07 International Business Machines Corporation Controlling the state of duplexing of coupling facility structures
US9860315B2 (en) 1998-09-10 2018-01-02 International Business Machines Corporation Controlling the state of duplexing of coupling facility structures
US7940706B2 (en) 2001-10-01 2011-05-10 International Business Machines Corporation Controlling the state of duplexing of coupling facility structures
US8341188B2 (en) 2001-10-01 2012-12-25 International Business Machines Corporation Controlling the state of duplexing of coupling facility structures
US10491675B2 (en) 2001-10-01 2019-11-26 International Business Machines Corporation Controlling the state of duplexing of coupling facility structures
JP2009134771A (en) * 2005-12-01 2009-06-18 Sony Computer Entertainment Inc Technology for implementing atomic compare and swap instruction using specific processor
JP2012531682A (en) * 2009-12-22 2012-12-10 インテル・コーポレーション SIMD vector synchronization
JP2014059902A (en) * 2009-12-22 2014-04-03 Intel Corp Synchronizing simd vectors
US8996845B2 (en) 2009-12-22 2015-03-31 Intel Corporation Vector compare-and-exchange operation
JP2020506483A (en) * 2017-02-08 2020-02-27 エイアールエム リミテッド Compare and swap transaction

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