JPS6021621A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To attain low power consumption and high speed driving for a load by replacing an inverter circuit with a push-pull buffer circuit in an MOS integrated circuit driving the load of large capacity and dividing an output section. CONSTITUTION:When an input signal to an input terminal 1 changes from a high level to a low level, transistors (TRs) T13, T15, T17, and T19 are nonconductive and a gate of a TR14 is changed into a high level, then a potential at an output terminal O is increased to the high level. Further, the source potential of a TR16 is also increased and the push-up effect of the capacitor C11 causes the drain voltage of the TRs T12, T14 to be increased, resulting that the potential increase of the terminal O is increased. Thus, a load capacitor C13 is charged. Since the output section is divided into two; TRs T16, T17 and T18, T19, the increase in the source potential of the TRT14 is quickened further.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that drives a large capacity load with low power consumption and at high speed.

In recent years, MO8 type integrated circuits have become popular with C
It is divided into MO8 integrated circuits and high-speed operation, high-density N-channel MO8 integrated circuits.

However, even in the field of N-channel MO8, lower power consumption is required while maintaining these characteristics.

The parts that consume a large amount of power in the N-channel MO8 integrated circuit are the clock signal drive circuit and the ROM.

This is a part that needs to operate a large capacity load such as a drive circuit for an address signal of a memory such as a RAM, a deduper circuit, etc. at high speed.

Many attempts have been made to increase the speed and reduce power consumption of this type of circuit. Among these, one that is particularly effective is the bootstrapping circuit proposed in Japanese Patent Application No. 54-64444.

FIG. 1 shows the circuit disclosed in Japanese Patent Application No. 54-64444.

In FIG. 1, the drain and gate of the enrichment transistor T1 are connected to the power supply terminal VCC, and the source is connected to the drain of the depletion type MO8) transistor T2 and to one end of the coupling capacitor C1.

The gate and source of T2 are connected to each other and to the drain of enhancement type MO8) transistor T3 and the gate of enhancement type MO8) transistor T4. The gate of T3 is connected to input terminal 1, and the source is grounded. The drain of T4 is VCC
The source is connected to the other end of 01, the output terminal O, and the enhancement type MOS transistor T5.
connected to the drain of The gate of T5 is connected to the ground, and the source is grounded. C2 is the load capacitance that this circuit should drive.

Next, let's look at the operation of the conventional circuit shown in Figure 1 in detail! Explain to i'[. The case of N-channel MO8 will be explained. Vc
c is a positive power supply. When the 11= signal that is input less than I is at a high level, T3. Since the gate of T5 becomes a low level, T4 is not conductive and a low level is output to the output terminal 0.

In this state, TI, T2. The current flowing through T3 for 1 m becomes the current consumption. Here, the potential across CI is T
The end connected to the source of TI increases the drive capability of TI to T
If the design is much larger than the drive capacity of 2, the VC
It is at a potential lower than C by the fall voltage of pTl, and
The end connected to the output terminal O is at ground potential.

Here, when the input signal (2) changes to low level, 13 becomes non-conductive and the gate of T4 is charged to high level. 1. In addition, since the gate of T5 also becomes low level, T5 becomes non-conductive. As a result, the potential of the output terminal O rises due to the charging current flowing from T4. The rise in the potential of the terminal O at this time causes a rise in the drain voltage of T2 to which one end of 9C1 is connected due to the pushing up effect of C]. This further increases the gate voltage of T4 through T2.

Therefore, T4) becomes more strongly conductive, and by repeating this process, the drain voltage of T2 and the gate voltage of T4 rise to twice the power supply potential minus the threshold voltage of T1, and The potential of terminal O becomes the power supply potential. That is, ■
4, when the number changes from high level to low level,
The potential difference between the north gate of T4 (about 11L of power supply - T
Since the load capacitance C2 can be charged while being maintained at a threshold voltage of 1), it is possible to charge the load capacitor C2 at high speed even if C12 is large. Also, if charging is completed and the power supply potential is 0, T3. Since T5 is non-conductive, no current flows through it, and the current consumption can be reduced to 0.

Next, when the signal applied to HC changes from low level to high level, T3. Since T5 is conductive and the gate of T4 is at ground potential, it is not conductive, and the potential of ◇ decreases through T5 at the ground potential. At this time, the potential of the end of C1 connected to the source of T1 is also 'r2. It decreases to (power supply potential - threshold voltage of TI) through T3.

As described above, the conventional circuit shown in Fig. 1 can charge and discharge a large capacity at high speed with low power consumption, but when the load capacitance C2 is very large, for example, several tens of pF, Because it is necessary to charge the T2. This means an increase in the load capacity of the impark circuit made up of T3, and it is important to note that the charging speed of the gate of T4 greatly affects the switching speed of the entire circuit.
Cru.

The purpose of the present invention is to improve the conventional circuit shown in FIG.
Another object of the present invention is to provide a circuit that can drive a large capacity load at high speed with low power consumption.

According to the present invention, a first insulated gate field effect transistor whose drain is connected to a source terminal, and a power input terminal connected to a terminal of the first insulated gate field effect transistor, an inverter circuit comprising a field-effect transistor connected to the depression-type insulated gate 1 to which a signal is inputted from the input terminal; and an enhancement-type insulated-gate field-effect transistor connected in series thereto;
a depletion-oscillating second insulated gate field effect transistor having a drain connected to the source of the insulated gate field effect transistor and a gate connected to the output of the inverter circuit; The third insulating gate 1E field-effect transistor is connected to the source of the effect transistor, the gate is connected to the input terminal, the source is grounded, and the drain is connected to the power supply terminal, and the gate is connected to 011 A fourth gate field effect transistor connected to the source of the second insulated gate field effect transistor and a drain connected to the source of the fourth insulated gate field effect transistor lLgf4
'N') C, the gate is connected to the input terminal, and the source is grounded.
The gate 'tortoise field effect transistor' and the drain are connected to the electric θ type terminal^2. and the gate is connected to the source Q' of the second transistor t2, so that the gate is connected to the insulated gate field effect transistor of 6, and the train is connected to the insulated gate field effect transistor of 6. A, it is connected to the north of the transistor, and the gate is configured as an input terminal,
The source of the first assembled gate field effect transistor is constructed of a seventh enhancement type insulated gate field effect transistor connected to the source and one capacitive element, and the source of the first assembled gate field effect transistor is To you, 1) C was done;
A semiconductor circuit is obtained in which the other end is connected to the source of the fourth insulated gate field effect transistor, and the source of the sixth insulated gate field effect transistor is connected to the output terminal.

Next, using the circuit of FIG. 2 which is an embodiment of the present invention, the structure and operation of the invention will be explained in detail in Section K (11) assuming that the circuit is composed of N-channel LV OS transistors.

The drain and gate of the enhancement type M6S transistor T11 are connected to the power supply terminal VccK, and the source is connected to the drain of the depletion type MOS transistor T12, the drain of the depletion type MO8) transistor T14, and -4 of the capacitive element C1l. The gate and source of T12 are connected to each other and to the drain of the gate enhancement type MO8) transistor T13 of T14. The gate of T13 is connected to input terminal 1, and the source is grounded. The drain of enhancement type MOi-3) transistor ff15 is grounded to the source of T14, and the enhancement type MOi-3)
It is connected to the gate of the MOS transistor 16.

The gate of TI5 is connected to the input terminal R4-C, and the source is grounded. Enhancement MO8) The drain of transistor T16 is connected to VCC, and the gate is connected to TI4.
The source is connected to the source of the enhancement type MO8) transistor T17, and the source is connected to the drain of the enhancement type transistor T17. It is connected to the other end of IC11.

The gate of 'f17 is connected to the input terminal, and the source is grounded. Enhancement gMO8) Transistor T1
The drain of B is connected to Vcc, the gate is connected to the source of T14, and the source is the enhancement gMO8)
It is connected to the drain of transistor T19 and also to output terminal 0. The source of T19 is connected to the input terminal, and the source is grounded.

C12 represents a load capacitance due to a diffusion layer attached to the source of 116, and C13 represents a load capacitance to be driven by this circuit. CI2<C13.

The circuit of the present invention is characterized by T2.
Inverter circuit fx'■"12°T1 consisting of T3
Inverter circuit composed of 3 and T14゜T15
Fl was replaced with a push-pull buffer circuit composed of T4. The output section by T5 is connected to T16. T17 and T18
．． This is where T19 is divided into two parts.

First, when the signal input to the input terminal is at a high level, T13. T15. T17. T19 is in conductive state, T14. T16. Since the gate of T18 is in the grounded state, T18 becomes non-conductive and the 7- position of the output terminal 0 becomes the ground potential. The current consumption at this time is from Tll to T12. T1
3 and the current flowing through T14. T] is the sum of the currents flowing through 5. Also, -! of C1l connected to the source of Tll! A voltage of 1゛W is a threshold voltage of Vcc-1'l1.

Here, when the input signal changes from high level to low level, T13. T15. T]7. '1' 19 becomes non-conductive and the gate of T14 changes to high level, so T1
6. The gate of T18 also becomes high level, T16°T18
is 4i, +IIj−f. As a result, the potential of the output terminal O also rises to a high level. The potential of the source of Xft'16 also rises, causing an increase in the voltage of T12°T14 due to the pushing up effect of C11. As a result, T12 is increased once to further increase the foot potential of 'r14. Therefore, the source voltage of T14 increases and T16
．． 'II'16 causes an increase in the foot potential of T18.
゜T18 driving ability? If is increased, the potential rise at terminal 0 is accelerated. In this way, the load capacitor C13 can be charged while the potential difference between the source and gate of T18 is maintained at approximately the threshold voltage of cc-421. In this work, the five examples shown in Figure 2 are the first.
The difference from the conventional example shown in the figure is 'i'16. 'r18 is driven by the gate level of T14 which is at a much higher potential than the source potential of T14.
The advantage is that the charging speed of 18 gates can be faster than that of the conventional example if the power consumption is the same. Also, there is one more thing: T4 in FIG. In this example, T5 is replaced by T16. T
17 and T18. This is the difference between T19 and T19.

The load capacity C12 attached to the source of T16 connected to C1l is much smaller than the negative capacity type C13 of 18 for output. For this reason, the C]20 charging speed is extremely fast. This means that the source of Tll due to the pushing effect of C1l, T12. The drain voltage of T14 rises quickly<
It means to do l”x.
16. The gate potential of T18 and the source potential of T14 can be increased even more quickly. Regarding the above two points, the detailed example of the present invention has advantages over the mirror 91.

When the input from ■ changes from low level to high level, T13. Ti5. T17. T19iQ4JriiL
, T14 gate 1χ and T16. If the gate potential of T18 is not the ground potential, 4. T16. T18 becomes non-conductive. The charges stored in C12 and C13 are T
17° T19 flows to the ground, and 0 becomes the ground potential. The switching speed at this time does not change much from the conventional example.

In addition, in the explanation of the implementation of "Kihatsu" in Figure 2, T1
1. T16. Although T18 is an enhancement-type edge OS transistor, T11 may be any MOS transistor that has the characteristic of becoming non-conducting when the gate and source power supply voltages are applied to the tube straight potential. It is more effective to use a MOS transistor whose voltage is almost OV or slightly on the depletion side.Also, for T16.TlB, considering power consumption, use a MOS transistor whose threshold voltage is almost OV or slightly on the depletion side like Tll ) It is better to use a transistor.

However, in Fig. 2, by connecting ■Cc to a signal terminal different from I, which is the gate of Tll, and applying a signal to ground the gate of Tll when the circuit of the present invention is not operating, It is possible to further reduce power consumption.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a circuit of a conventional example (%Application No. 54-64444), and FIG. 2 is a diagram showing a circuit of an embodiment of the present invention. Tll, T13. T15. T16. T17. TlB,T
19...Enhancement type transistor,
'I'12. T14...Depression type transistor, C11, C12°C13...-Capacitance. Agent Patent Attorney Uchihara 3m ・' IJ , , 1

Claims (1)

[Claims] a first end of a depletion type connected between the other end of the load means and a reference potential;
a first series circuit having a field transistor of W and a second transistor of W; a third series circuit of depletion type connected between the other end of the load means and a reference potential;
a second series circuit having a field effect transistor and a fourth enhancement type field effect transistor; a third series circuit having fifth and sixth enhancement type field effect transistors; and the other end of the load means. and third
a capacitor connected between the intermediate connection point of the second series circuit and the gate of the fifth transistor; 4th and 6th
means for applying an input signal to the gate of the transistor;
A semiconductor circuit characterized as IPf@ having means for connecting an intermediate connection point of the first series circuit and a gate of a third transistor.