JPS59231916A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To drive a large capacity of load with low power consumption by providing an inverter circuit and a push-pull buffer circuit using an insulation gate field effect transistor (TR) and a depletion insulation gate field effect TR. CONSTITUTION:Enhancement MOS TRsT21, T23, T25-T27 and depletion MOSTRs T22, T24 are used, an signal input is applied to an input terminal I and a power supply is applied from a power supply terminal Vcc. The TRT22 and T23 constitute an E/D inverter circuit and the TRT24, T25 constitute an E/D push-pull buffer circuit. Then the TRT26, T27 are charged so as to drive a capacitive element C22 connected to an output terminal O. Thus, the semiconductor circuit driving a large capacity of load in high speed with low power consumption is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor circuits, and particularly to a circuit that drives a large load capacity at high speed with low power consumption.

In recent years, there has been a strong demand for lower power consumption in integrated circuits (
,0 Although there is a remarkable trend toward the adoption of MO8 technology, it is still the case that N
Mainly channel MOS. However, even in fields where N-channel MOS is the main component, it is necessary to reduce power consumption while maintaining its characteristics. In an integrated circuit using an N-channel MO8, the parts that consume a particularly large amount of power are the black and red signal drive circuits, memory (ROM, RAM, etc.) address signal drive circuits, memory address decoders, etc. This is a circuit part that needs to charge and discharge a large load capacity extremely quickly.

In the past, many attempts to speed up and reduce power consumption of circuits for this type of purpose have been announced, and each has shown its effectiveness quickly. The circuit which has an outstanding effect in terms of power is patented in 1983-1986
444 Pootstrap buffer circuit.

FIG. 1 shows the circuit of the embodiment of the above-mentioned Japanese Patent Application No. 54-64444 as a conventional example.

In FIG. 1, the drain and gate of the enhancement type MOS transistor Tll are connected to the power supply terminal voolc.
The source is connected to one end of the coupling capacitor ftc11, and the depletion type MOS transistor T
Connected to the drain of 12.

The gate and source of T12 are connected to each other and to the gate of the enhancement type MO8) run lister T14 and the drain of the enhancement type MO8) run lister T13. The gate of T13 is connected to the signal input terminal l, and the source is grounded. The drain of T14 is connected to V(loK), and the source is connected to the other end of C1l, and is also connected to the drain of enhancement type MOS transistor T15, and is also connected to the output terminal OK.The gate of T15 is connected to is,
Source is grounded. C12 indicates the load capacitance to be driven by this circuit.

Next, the operation of the conventional circuit shown in FIG. 1 will be explained in detail. For convenience of explanation, it is assumed that the MOS) run lister is an N-channel, so CC is assumed to be a positive power supply. ■When the input signal is at high level, T
13 and Tzs are in a conductive state, and since a low level is applied to the gate of T14, T14 is in a non-conductive state. Therefore, the potential of the output terminal O becomes low level.

In this state, T11. T12. The current flowing through T13@ becomes current consumption. Considering the potential at both ends of C1l, the end connected to the source of T11 is designed so that the driving ability of Tll is much larger than that of T12, so the threshold voltage of Tlt is raised from the power supply potential. j) The other end of tCll, that is, the end connected to output terminal 0, is at ground potential. Here, when the input signal from ■ changes to low level, T13 immediately becomes non-conductive.J), T14
gate is charged to high level. On the other hand, since the gate of T15 goes to low level, T15 also becomes non-conductive.

As a result, the potential at 0 rises due to the charging current flowing through T14, but the rise in potential at 0 is transmitted to the drain of T12 via C11' (l-), and further through T12 to the potential at the gate of T14. To that end, T1
By repeating this loop, the potential of the end of cll connected to the source of T11 and the potential of the gate of T14 become the power supply voltage. The voltage rises to a potential equal to twice the threshold voltage of Tll, and the potential at the 0 point becomes the power supply potential. That is, when the signal given from ■ changes from high level to low level, the potential difference between the source and gate of T14 is (
The load capacitance C is maintained at the power supply potential - Tll threshold voltage).
Since l2f charging is possible, high-speed charging is possible even if C12 is large. Also, after charging is completed and 0 becomes the power supply potential, T13 and T15
Since is non-conducting, there is no current flowing through 1,
Current consumption is zero.

Next, when the signal input applied to ■ changes from low level to high level again, T13 and T15 become conductive, and T14 becomes non-conductive because its gate drops to the ground potential, and the potential of 0 becomes As a result, it drops to ground potential. At this time, the potential of the end of C11 connected to the source of Tll also decreases through T12 and T13 to a value obtained by subtracting the threshold voltage of Tll from the power supply potential.

As mentioned above, the conventional circuit shown in FIG. 1 consumes low power and is capable of charging and discharging a large capacity at high speed.
If the load capacitance C12 is very large, for example several pp. This means that the load capacity of
The speed of charging the gate of T14 occupies a large proportion of the switching speed of the entire circuit, and the overall switching speed also becomes slow.

The purpose of the invention is to improve the conventional circuit shown in FIG.
Another object of the present invention is to provide a semiconductor circuit that can drive a large capacity load at high speed with low power consumption.

An inventive semiconductor circuit includes a first insulated gate field effect transistor having a drain connected to an electrolytic terminal;
a depletion type second insulated gate field effect transistor in which the drain is connected to the source of the insulated gate field effect transistor, and the gate and the source are connected to each other; a third insulated gate field effect transistor of an enhancement type, the gate of which is connected to the input terminal, the source of which is connected to the ground terminal, and the drain of which is connected to the source of the first insulated gate field effect transistor; a dipline type fourth insulated gate field effect transistor having a gate connected to the source of the second insulated gate field effect transistor, and a drain connected to the source of the fourth insulated gate field effect transistor; , an enhancement type fifth insulated gate field effect transistor having a gate connected to the input terminal and a source connected to the ground terminal; and a drain connected to the power supply terminal and the fourth insulated gate field effect transistor.

the sixth connected to the source of the gate field effect transistor;
an enhancement type seventh insulated gate whose drain is connected to the source of the sixth insulated gate field effect transistor, whose gate is connected to the input terminal, and whose source is connected to the ground terminal. and a capacitive element inserted between the source of the first insulated gate field effect transistor and the source of the sixth insulated gate field effect transistor, the sixth insulated gate field effect transistor It is characterized in that the source of the transistor is connected to the output terminal.

Next, referring to FIG. 2, which is a circuit diagram of an embodiment of the present invention, the structure and operation of the present invention will be explained in detail assuming that it is constructed of N-channel MOS transistors.

Enhancement gMO8) The drain and gate of the run lister T21 are connected to the power supply terminal V. 0, the source is connected to the drain of the depletion type MO8) run lister T22 and the drain of the depletion type MO8) run lister T24
, and also connected to one end of the capacitive element T21. The gate and source of T22 are connected to each other, as well as to the gate of T24 and the drain of an enhancement type MO8) run lister T23. The gate of T2a is connected to the signal input terminal I, and the source is grounded. Enhancement type M
O8) The drain of the run lister T25 is connected to the source of T24, and is also connected to the gate of the enhancement type MO8) run lister T26, the gate is connected to the input terminal ■, and the source is grounded. The drain of T26 is connected to VOO, and the source is an enhancement type MO
8) Connected to the drain of transistor T27, and also connected to the other end of C21, and also connected to output terminal O. The gate of T27 is connected to ■, and the source is grounded. C22 indicates the load capacitance to be driven by this circuit.

The feature of the circuit of the present invention is that the EID type inverter circuit composed of T12 and T13 of the circuit of the embodiment shown in FIG. Focusing on the possibility of replacing it with an E/D type push-pull buffer circuit configured with
This is because the driving capacity has been increased.

First, when the signal input to input terminal I is at high level, T23. T25 and T27 are in conduction state, T
Since the gates of T24 and T26 are at the ground potential, T26 is non-conductive and the potential of the output terminal O is at the ground potential. The current path from VOO to ground in this state is from T21 to T22 and T23.
'i the path that flows through and from T21 to T24 and T2
There are many paths that flow through 5i, and the sum of the paths is the current consumption. Also, the end of %C21 connected to the source of T21 has a potential equal to the power supply potential minus the threshold voltage of T21, as in the conventional circuit shown in FIG.

Here, when the input signal changes from high level to low level, T23. T25. T27 should be non-conductive.

The potential of the gate of T24 is at high level, and as a result, the potential of the gate of T26 is also at high level, so T26
becomes conductive, and the potential of the output terminal O also shifts to high level. This change in the potential of O causes an increase in the potential at the connection point between the source of T21 and the drains of T22 and T24 through C21, and T24 through T22i.
increase the gate potential of As a result, through T24'i, an increase in the drain potential of T24 causes an increase in the source potential of T24, that is, the gate potential of T26, and T
26 is increased, and the potential rise of 0 is further accelerated. Can be charged.

In this operation, the circuit shown in FIG. 2 differs from the conventional circuit shown in FIG.
Therefore, if the power consumption is the same, the rate at which the gate of T26 is charged is 1.5~1.
For example, in the conventional circuit shown in Fig. 1, if the power supply is 5 mm and the load capacitance C12 is 1
When configured using an N-channel silicon gate field effect transistor with a gate oxide film thickness of 500λ and a channel length of 3μ, with a current consumption of 0 pF and a current consumption of 100 μA.

T after the input signal changes from high level to low level
It takes 2Qns for the gate potential of 14 to rise to 4■,
15n more until the potential of output terminal 0 rises to 4.5V
s, a total switching time of 35 ns was required, but according to the circuit according to the embodiment of the present invention shown in FIG.
Assuming that the total current flowing through T26 is 100 μA and all other conditions are the same, it takes 10 ns from when the input signal changes from high level to low level until the gate potential of T26 rises to 4.5 μA.

12 more times until the potential of output terminal 0 rises to 4.5■
ns, a total switching speed of 22 ns, and when comparing the circuit as a whole, an improvement in switching speed of about 1.6 times was obtained with the same power consumption and the same load capacity.

When the input from ■ changes from low level to high level, T2B, T25. T27 becomes conductive, the gate potential of T24 and the gate potential of T26 drop to the ground potential, and T26 becomes non-conductive, so the charge stored in 022 flows to the ground through T27'i.

0 is the ground potential. The switching speed in this case is almost unchanged from the conventional circuit shown in FIG.

As mentioned above, the semiconductor circuit of the present invention is an optimal circuit for driving a large capacity load at high speed with low power consumption, and its effect is superior to that of the conventional circuit shown in Figure 1. is clear.

In addition, in the explanation using the circuit of the embodiment of the present invention in FIG. 2, T21 and T26 are enhanced men L type MO8).
Although T21 is a run resistor, it only needs to be an insulated gate field effect transistor that is non-conductive when a power supply voltage is applied to the gate and north with respect to the substrate potential, so the threshold voltage is OV or slightly It tends to be more effective if it is on the depletion side. Although there is no problem in circuit operation even if a depletion MO8) run lister is used for T2O, it is more effective if the threshold voltage is OV or slightly on the depletion side in terms of power consumption and switching speed.

In addition, in FIG. 2, the gate of T21 is ■. .

However, when the gate of T21 is connected to a signal terminal different from I, and the entire circuit is not operated, T21 is
It is also possible to further reduce power consumption by setting the gate of the circuit to the ground potential.

14. Brief Description of the Drawings FIG. 1 is a diagram showing a circuit of a conventional example (Japanese Patent Application No. 1983-64444), and FIG. 2 is a diagram showing a circuit of an uninvented embodiment.

T21. T23. T25. T2O, T27・Mountain・Enhancement type MO8) Run lister, T22. T2
4... Depletion type MOS transistor, C21, C22... Capacity.

,・;・:5. ,,;::;＼ Agent: Patent Attorney Uchihara Shin 1'; 5'

Claims (1)

[Claims] a first insulated gate field effect transistor whose drain (or source) is connected to a power supply terminal; and a first insulated gate field effect transistor whose drain (or source) is connected to the source (or drain) of the first insulated gate field effect transistor; (
or a depletion type second insulated gate field effect transistor whose drains are connected to each other;
an enhancement type third insulated gate whose drain (or source) is connected to the source (or source) of the insulated gate field effect transistor, whose gate is connected to the input terminal, and whose source (or drain) is connected to the ground terminal; a field effect transistor; a drain (or source) connected to the source (drain) of the first insulated gate field effect transistor; and a gate connected to the source (drain) of the second insulated gate field effect transistor; a fourth insulated gate field effect transistor of the application type; a drain (or source) connected to the source (or drain) of the fourth insulated gate field effect transistor; a gate connected to the input terminal; (
an enhancement type fifth insulated gate field effect transistor whose drain (or drain) is connected to a ground terminal; and a source (or source) of the fourth insulated gate field effect transistor whose drain (or source) is connected to a power supply terminal and whose gate is a sixth insulated gate field effect transistor whose drain (or source) is connected to the source (or drain) of the sixth insulated gate field effect transistor and whose gate is connected to the input terminal; , an enhancement type seventh insulated gate field effect transistor whose source (or drain) is connected to a ground terminal, and a source (or drain) of the first insulated gate field effect transistor and the sixth insulated gate field effect transistor. The sixth insulated gate field effect transistor is characterized in that the sixth insulated gate field effect transistor has a source (or drain) connected to an output terminal. semiconductor circuit.