JPS6021547A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6021547A JPS6021547A JP58127900A JP12790083A JPS6021547A JP S6021547 A JPS6021547 A JP S6021547A JP 58127900 A JP58127900 A JP 58127900A JP 12790083 A JP12790083 A JP 12790083A JP S6021547 A JPS6021547 A JP S6021547A
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- area
- mounting
- plate
- copper foil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
トランジスタ、サイリスタ等の中、小電力用の半導体装
置の外囲器構造に係り、特に耐湿性レベルを改良した樹
脂封止放熱板付絶縁形半導体装置。[Detailed Description of the Invention] [Technical Field of the Invention] An insulated semiconductor device with a resin-sealed heat dissipation plate, which relates to the envelope structure of a medium to low power semiconductor device such as a transistor or thyristor, and which has particularly improved moisture resistance level. .
に関する。Regarding.
樹脂封止形半導体装置の信頼性項目のうち、最も重要な
ものは耐湿性である。リードフレームと樹脂界面、又放
熱板付のものでは放熱板と樹脂界面が、それぞれの材料
の熱膨張係数の差により、水分侵入経路の主なものと考
えられている。従来の方法による樹脂封止放熱板付半導
体装置を例として以下説明する。Among the reliability items of resin-sealed semiconductor devices, the most important one is moisture resistance. The interface between the lead frame and the resin, or the interface between the heat sink and the resin in the case of a heat sink with a heat sink, is considered to be the main route for moisture intrusion due to the difference in the coefficient of thermal expansion of each material. A semiconductor device with a resin-sealed heat sink formed by a conventional method will be described below as an example.
耐１図は従来例のダーリントントランジスタアレイ樹脂
封止放熱板イ」絶縁形半導体装置の外観図で、同図（ａ
）は平面図、同図（ハ）は正面図である。第２図は第１
図に示す半導体装置の内部構造図であって説明のためモ
ールド樹脂を取り除いた状態を図示しである。第６図は
第１図に示す半導体装置の電気回路図である。なお各図
において同一部分には同一符号を使用する。１は放熱板
、２は本半導体装置を外部取付板等に取り伺けるための
取付穴、３は樹脂封止後保持枠等不要となった部分を切
断除去し整形されたリードフレーム、４はモールド樹脂
である。半導体素子８はこの従来例ではダーリントント
ランジスタチップで、該素子８はリードフレーム３のチ
ップマウントランド７を介して放熱板１の半導体素子を
搭載するための工＋）アロに半田付される。第４図は従
来例の放熱板を示し、同図（ａ）は平面図、（ト）は右
方側面図、（Ｃ）はＡ−Ａ’断面図、（ｄ）は正面図、
（ｅ）は下面図である。放熱板はアルミニウム板又は銅
板に絶縁接着剤を使用して銅箔を貼り伺けた基板、例え
ばＨＩＴＴプレート（デンカ社商品名）を基材として使
用する。Figure 1 is an external view of a conventional Darlington transistor array resin-sealed heatsink insulated semiconductor device.
) is a plan view, and (c) is a front view. Figure 2 is the first
2 is a diagram of the internal structure of the semiconductor device shown in the figure, with the molding resin removed for illustrative purposes; FIG. FIG. 6 is an electrical circuit diagram of the semiconductor device shown in FIG. 1. Note that the same reference numerals are used for the same parts in each figure. 1 is a heat dissipation plate, 2 is a mounting hole for attaching this semiconductor device to an external mounting plate, etc., 3 is a lead frame that has been shaped by cutting off unnecessary parts such as the holding frame after resin sealing, and 4 is a shaped lead frame. It is mold resin. In this conventional example, the semiconductor element 8 is a Darlington transistor chip, and the element 8 is soldered to the heat dissipation plate 1 for mounting the semiconductor element via the chip mounting land 7 of the lead frame 3. FIG. 4 shows a conventional heat sink, in which (a) is a plan view, (g) is a right side view, (c) is a sectional view taken along line A-A', and (d) is a front view.
(e) is a bottom view. The base material of the heat dissipation plate is an aluminum plate or a copper plate on which a copper foil is attached using an insulating adhesive, such as a HITT plate (trade name of Denka Corporation).
第４図に示すように半導体素子を搭載するためのエリア
６（斜線部分）を除いた銅箔面はエツチングにより銅箔
が除去され、絶縁層２０が露出したパターンとなってい
る。放熱板の外周の一部は両面又は片面がプレスにより
潰される。この潰し部５は樹脂封止後樹脂と放熱板との
密着度を良くし、水分侵入経路を長くして、樹脂と放熱
板との界面の耐湿性を向上するために設けられる。第５
図はリードフレームで銅系素材例えばＫＦＣ（神戸製鋼
商品名〕の厚さ０５πｍ′ｆ：エッチング加工等して作
られる。第５図（ａ）はリードフレーム１連（チップマ
ウントランド７を４個持つ〕の平面図、同図ワはチップ
マウントランド７の拡大平面図、同図（Ｃ）はＢ −Ｂ
’線断面の段差部分の拡大図である。チップマウントラ
ンド７は半導体素子を搭載するための領域で、アウター
リード部１１との間に段差が生ずるよう第５図（Ｃ）に
示すごとく、チップマウントランド７はアウターリード
部１１の面より０．５５ｍｙｙ下げるように曲げ加工さ
れる。１３はダイオードマウント用パッドである。−１
，タチップマウントラン３−
ド及びダイオードマウント用パッドのそれぞれのインナ
ーリード部１２の半導体搭載側の面には、耐湿性を良く
するためプレス加工によりＶ溝が設けられている。第４
図に示す放熱板の半導体を搭載するためのエリア６と第
５図に示すリードフレームのチップマウントランド７と
が一致するように、放熱板の上にリードフレームを重ね
、エリア６にチップマウントランド７を半田付等で接着
する。As shown in FIG. 4, the copper foil is removed by etching from the copper foil surface except for area 6 (shaded area) for mounting a semiconductor element, resulting in a pattern in which the insulating layer 20 is exposed. A portion of the outer periphery of the heat sink is crushed on both sides or on one side by pressing. This crushed portion 5 is provided to improve the degree of adhesion between the resin and the heat sink after resin sealing, to lengthen the moisture intrusion path, and to improve the moisture resistance of the interface between the resin and the heat sink. Fifth
The figure shows a lead frame made of a copper-based material such as KFC (Kobe Steel product name) with a thickness of 05πm'f: etching, etc. Figure 5 (a) shows one lead frame (4 chip mount lands 7 (C) is an enlarged plan view of the chip mount land 7.
It is an enlarged view of a stepped portion of a line cross section. The chip mount land 7 is an area for mounting a semiconductor element, and as shown in FIG. It is bent to lower it by .55 myy. 13 is a diode mounting pad. -1
, a V-groove is formed by press processing on the semiconductor mounting side surface of each inner lead portion 12 of the chip mount land 3 - pad and the diode mount pad in order to improve moisture resistance. Fourth
Lay the lead frame on the heat sink so that the area 6 of the heat sink shown in the figure for mounting the semiconductor and the chip mount land 7 of the lead frame shown in FIG. Attach 7 by soldering, etc.
これにより放熱板付絶縁形リードフレームが得られる。As a result, an insulated lead frame with a heat sink is obtained.
このリードフレームのチップマウントランド７に半導体
素子８を、又ダイオードマウント用パッド１６にダイオ
ード９をそれぞれ半田付等で接着し、次にワイヤボンデ
ィング１０シて図６に示す電気回路を得る。さらにエン
キャップ樹脂を使用し半導体素子８及びダイオード９の
周辺部をおおった後、モールド樹脂（エポキシ系）でト
ランスファーモールドにより樹脂封止し、リードフレー
ムの保持枠等切断除去し、整形して第１図に示すダーリ
ントントランジスタアレイ樹脂封止放熱板付絶縁形半導
体装置が得られる。A semiconductor element 8 is bonded to the chip mount land 7 of this lead frame, and a diode 9 is bonded to the diode mount pad 16 by soldering or the like, and then wire bonding is performed to obtain the electric circuit shown in FIG. Furthermore, after covering the periphery of the semiconductor element 8 and diode 9 using an encap resin, the resin is sealed with a mold resin (epoxy type) by transfer molding, the holding frame of the lead frame, etc. is cut and removed, and the parts are shaped and shaped. An insulated semiconductor device with a Darlington transistor array resin-sealed heat sink shown in FIG. 1 is obtained.
４−
〔背景技術の問題点〕
樹脂封止放熱板付絶縁形半導体装置では耐湿性レベルを
高めることが信頼度向上には重要な問題であり、この点
に関し第１図の従来の半導体装置では前記のように放熱
板外周に潰し加工を施し耐湿性の向上をはかっているが
、従来の技術では第１図又は第２図に示すように取付穴
２周辺の放熱板１とモールド樹脂４との界面に潰し部を
設けることは構造上不可能で潰し部が欠けている。した
がって取付穴２の周辺部の放熱板１とモールド樹脂４と
の界面を通り内部に侵入する水分を防ぐことはできない
し、またこの部分の放熱板１とモールド樹脂４との密着
性は、その他の放熱板外周に潰し加工が施しである部分
に比べればはるかに劣る。該半導体装置の耐湿性レベル
を向上するためには、取付穴の周辺部からの水分の侵入
を防ぐことが重要な問題点である。4- [Problems with the Background Art] In an insulated semiconductor device with a resin-sealed heat sink, increasing the moisture resistance level is an important issue for improving reliability.In this regard, the conventional semiconductor device shown in FIG. As shown in Figure 1 or Figure 2, the outer periphery of the heat sink is flattened to improve moisture resistance. It is structurally impossible to provide a crushed portion at the interface, and the crushed portion is missing. Therefore, it is not possible to prevent moisture from penetrating into the interior through the interface between the heat sink 1 and the molded resin 4 around the mounting hole 2, and the adhesion between the heat sink 1 and the molded resin 4 in this area cannot be prevented. It is much inferior to the part where the outer periphery of the heat sink is crushed. In order to improve the moisture resistance level of the semiconductor device, it is important to prevent moisture from entering from the periphery of the mounting hole.
この発明の目的は、□従来の樹脂封止放熱板付絶縁形半
導体装置において、前記のごとき問題点を解消し、放熱
板と→：−ルド樹脂との界面からの水分の侵入を防１に
し、面ｌ湿性レベルが向上した半導体装置を提供するこ
とである。The purpose of the present invention is to solve the above-mentioned problems in conventional insulated semiconductor devices with resin-sealed heat sinks, to prevent moisture from entering from the interface between the heat sink and the resin, and to An object of the present invention is to provide a semiconductor device with improved surface moisture level.
従来のアルミニウム板又は銅板と銅箔との間に絶縁物を
介してなる絶縁基板を用いた放熱板があり、かつ該銅箔
にｄ少ぐとも一つの半導体素子を搭載するためのエリア
を有するパターンが形成された放熱板を用い、該工ＩＪ
アに半導体素子を搭載し、樹脂封止してなる半導体装置
においては、モールド樹脂と接する放熱板外周の周辺部
の両面又は片面に潰し加工を施し、該部分の放熱板とモ
ールド樹脂との界面からの水分侵入の防止をはかってい
るが、外周の潰し部を構造上利用でき々い例えば図１の
取付穴周辺の放熱板とモールド樹脂との界面のごとき部
分が存在する。この部分の放熱板面にコイニング加工を
施し、外周潰し部と等しい効果を得ることが考えられる
が、本発明のごとく絶縁基板を使用する場合−１、コイ
ニング加工により放熱板の絶縁層が破損され、絶縁耐圧
を保持でき々いおそれがあり、コイニング加工を採用す
ることはできない。本発明は前記第１図の取伺孔周辺の
ごとく外周の潰し部を設けることのできない部分の放熱
板面」二に銅箔の帯状パターンをエツチング加工により
形成し、該帯状の銅箔パターンと放熱板外周の両面又は
片面の潰し部とにより半導体素子を搭載するためのエリ
ア周囲を包囲する例えば第６図のごとき放熱板を使用し
たことを特徴とする。帯状銅箔パターンの幅はエツチン
グ加工によゆ０．２〜Ｑ、 ３ ｍＷ程度まで細くでき
、かつ多重に設けることにより、また銅と樹脂との密着
性が良好であることにより、従来の方法に比べより高い
耐湿性レベルが確保できる。There is a heat sink using an insulating substrate formed by interposing an insulator between a conventional aluminum plate or copper plate and copper foil, and the copper foil has an area for mounting at least one semiconductor element. Using a heat sink with a pattern formed, the IJ
In a semiconductor device in which a semiconductor element is mounted on a substrate and sealed with resin, both sides or one side of the peripheral part of the heat sink that comes into contact with the mold resin is crushed, and the interface between the heat sink and the mold resin at that part is crushed. However, there are some parts, such as the interface between the heat dissipation plate and the molded resin around the mounting hole in FIG. 1, where it is difficult to utilize the collapsed part of the outer periphery structurally. It is conceivable to perform coining processing on the surface of the heat sink in this area to obtain the same effect as the crushed outer periphery, but when using an insulating substrate as in the present invention-1, the coining process may damage the insulating layer of the heat sink. , the coining process cannot be used because it may not be able to maintain the dielectric strength. In the present invention, a band-shaped pattern of copper foil is formed by etching on the surface of the heat dissipation plate in a portion where a crushed portion on the outer periphery cannot be provided, such as around the access hole shown in FIG. The present invention is characterized in that a heat sink as shown in FIG. 6, for example, is used, which surrounds an area for mounting a semiconductor element with a crushed portion on both sides or one side of the heat sink's outer periphery. The width of the band-shaped copper foil pattern can be made as thin as 0.2 to 3 mW depending on the etching process, and by providing multiple layers, and because the adhesion between copper and resin is good, it is possible to reduce the width of the pattern using conventional methods. A higher level of moisture resistance can be ensured compared to
なお本発明による帯状銅箔パターンが形成された放熱板
を用いて、これに半導体素子を搭載する場合、半導体素
子を搭載するためのチップマウントランドを設けた銅系
又は鉄系リードフレームを用い、該チップマウントラン
ドを介して放熱板の前記エリアに半導体素子を固着して
もよいし、又放熱板の前記工ＩＪアに直接半導体素子を
固着して７−
もよい。Note that when a semiconductor element is mounted on a heat sink on which a band-shaped copper foil pattern according to the present invention is formed, a copper-based or iron-based lead frame provided with a chip mount land for mounting the semiconductor element is used, The semiconductor element may be fixed to the area of the heat sink via the chip mount land, or the semiconductor element may be fixed directly to the IJ area of the heat sink.
図面を参照して実施例について説明する。従来例を示す
第１図（外観図〕、第３図（内部の電気回路図）および
第５図（リードフレーム）は本発明の実施例でも同一で
ある。第６図は本発明の実施例の放熱板を示し同図（ａ
）は平面図、（ト）は右方側面図、（ｃ）はｃ−ｃ’線
断面図、（ハ）は正面図、（ｅ）は下面図である。第７
図は放熱板の面付は図である。Examples will be described with reference to the drawings. Fig. 1 (outside view), Fig. 3 (internal electrical circuit diagram), and Fig. 5 (lead frame) showing the conventional example are the same in the embodiment of the present invention. Fig. 6 shows the embodiment of the present invention. The same figure shows the heat dissipation plate (a
) is a plan view, (g) is a right side view, (c) is a sectional view taken along line c-c', (c) is a front view, and (e) is a bottom view. 7th
The figure shows the mounting of the heat sink.
この放熱板の製造工程は次の通りである。第７図に示す
ように例えばＨＩ Ｔ Ｔプレート（デンカ社商品名）
の銅箔面側に前記エリア６と帯状銅箔パターン１４を配
設し、エツチング加工によりエリア６と帯状銅箔パター
ン１４を残して銅箔を除去する。The manufacturing process of this heat sink is as follows. As shown in Figure 7, for example, the HI T T plate (product name of Denka Co., Ltd.)
The area 6 and the strip copper foil pattern 14 are arranged on the copper foil surface side of the copper foil, and the copper foil is removed by etching leaving the area 6 and the strip copper foil pattern 14.
使用ＬｉＨ，ＴＴＴプレートは厚さ２朋のアルミニウム
を基板とし、絶縁層として高熱伝導性のエポキシ系接着
剤を用い、厚さ３５μｍの銅箔を接着したものである。The LiH, TTT plate used has an aluminum substrate having a thickness of 2 mm, and a copper foil having a thickness of 35 μm bonded thereto using a highly thermally conductive epoxy adhesive as an insulating layer.
帯族銅箔パターンの□幅は０．２〜０３闘で二重に設け
た。エツチング加工後放熱板の外形及び取付穴をプレス
加工するために設けたガイ８−
ド穴１５を放熱板１個に対して２穴あける。その後７ヤ
ーリ／グ加工により短冊に切断し、プレス加工により外
形抜きをする。更に耐湿性を確保するために設ける外周
両面の潰し加工を施し第６図に示す放熱板が得られる。The □ width of the band copper foil pattern was set twice to 0.2 to 0.03 mm. After the etching process, two guide holes 15 are made for each heat sink plate, which are provided to press the external shape of the heat sink plate and the mounting holes. After that, it is cut into strips using a 7-year/g process, and the outer shape is cut using a press process. Furthermore, in order to ensure moisture resistance, both surfaces of the outer periphery are crushed to obtain the heat sink shown in FIG. 6.
半導体を搭載するためのエリア６は外周の潰し部５と帯
状の銅箔パターン１４によって包囲されている。次にリ
ードフレームは従来例と同一の第５図に示すものを使用
する。An area 6 for mounting a semiconductor is surrounded by a crushed portion 5 on the outer periphery and a strip-shaped copper foil pattern 14. Next, the lead frame shown in FIG. 5, which is the same as the conventional example, is used.
第６図に示す放熱板の半導体を搭載するためのエリア６
と第５図に示すリードフレームのチップマウントランド
７とが一致するように放熱板の上にリードフレームを重
ね、エリア６にチップマウントランド７を半田付等で接
着し、放熱板付絶縁形リードフレームが得られる。以後
は従来例と同一の製造方法によりダーリントントランジ
スタアレイ樹脂封止放熱板付絶縁形半導体装置が作られ
る。Area 6 for mounting the semiconductor of the heat sink shown in Figure 6
The lead frame is stacked on the heat sink so that the chip mount land 7 of the lead frame shown in FIG. is obtained. Thereafter, an insulated semiconductor device with a Darlington transistor array resin-sealed heat sink is manufactured by the same manufacturing method as in the conventional example.
なお本例では帯状銅箔パターンは二重に設けたが多重に
することもでき又該パターン幅も変えられる。ＨＩＴＴ
プレート（デンカ社商品名）を使用したが、他のメーカ
ーが扱っているアルミニウム絶縁基板はもとより、アル
ミニウム板の代りに銅系材料であってもよい。！、た本
例ではダーリントントランジスタアレイということでト
ランジスタ素子４個、ダイオード２個ヲ１とめて扱って
いるが、トランジスタ素子１個でも、ダイオード１個で
も本発明を適用できる。In this example, the strip-shaped copper foil pattern is provided in double layers, but it can also be provided in multiple layers, and the width of the pattern can also be changed. HITT
Although a plate (trade name of Denka Corporation) was used, it is also possible to use an aluminum insulating substrate sold by other manufacturers, or a copper-based material instead of the aluminum plate. ! In this example, since it is a Darlington transistor array, four transistor elements and two diodes are treated as one, but the present invention can be applied to either one transistor element or one diode.
本発明のごとく放熱板に帯状の銅箔パターンを追設し、
該パターンと放熱板外周の潰し部とで、半導体素子を搭
載しているエリアを包囲するようにした樹脂封止放熱板
付絶縁形半導体装置では耐湿性が従来品に比し著しく向
上した。樹脂封止半導体装置のパッケージの耐湿試験の
加速試験として加圧蒸気中に放置するプ１／ッシャーク
ッカーテスト（以下ＰＣＴと略称する）がある。同一条
件（１２７℃、 ２．５ ａｔｒｎ 、 １００％ＲＨ
）でＰＣＴをおこなった結果について以下のべる。第２
図に示す従来の装置では、取付穴２の周辺より半導体素
子が搭載されているエリアまでの水分侵入経路に対する
考慮が乏しく、放熱板に銅板を使用した場合ＰＣＴレベ
ルで３０〜５０時間、また樹脂の膨張係数に近いアルミ
ニウム板を使用した場合でもＰＣＴレベルで１００時間
未満である。しかし本発明によるものはＰＣＴレベルで
１００時間以上の結果かえられた。As in the present invention, a strip-shaped copper foil pattern is added to the heat sink,
An insulated semiconductor device with a resin-sealed heat sink in which the pattern and the crushed portion on the outer periphery of the heat sink surround the area in which the semiconductor element is mounted has significantly improved moisture resistance compared to conventional products. As an accelerated moisture resistance test for a package of a resin-sealed semiconductor device, there is a Pu1/Sher Cooker Test (hereinafter abbreviated as PCT) in which the package is left in pressurized steam. Same conditions (127°C, 2.5 atrn, 100% RH
) The results of PCT are described below. Second
In the conventional device shown in the figure, there is little consideration given to the path of moisture intrusion from the vicinity of the mounting hole 2 to the area where the semiconductor element is mounted. Even when using an aluminum plate with an expansion coefficient close to , the PCT level is less than 100 hours. However, the method according to the present invention showed improved results at the PCT level for more than 100 hours.
また本発明の如く絶縁基板を使用する場合は、耐圧保持
の関係上コイニング加工は採用できないが、採用可能な
類似品のコイニング加工をした半導体装置ではＰＣＴレ
ベルで１００時間以上である。Further, when an insulating substrate is used as in the present invention, coining processing cannot be employed due to voltage resistance requirements, but similar semiconductor devices that can be used and which are subjected to coining processing have a PCT level of 100 hours or more.
したがって本発明の帯状銅箔パターンを設けることによ
りコイニング加工と同様な効果が得られる。Therefore, by providing the strip-shaped copper foil pattern of the present invention, the same effect as the coining process can be obtained.
第１図は樹脂封止放熱板付絶縁形半導体装置の外観図で
従来のものと本発明によるものと同一である。同図（植
、（ト）はそれぞれ平面図、正面図。第２図は第１図に
示す半導体装置の内部構造図でモールド樹脂を取り除い
である。同図（ａ） 、 （））ｌはそれ線断面図、正
面図、下面図。第５図はリードフレームで従来のものと
本発明によるものと同一であり、同図（ａ）〜（Ｃ）は
平面図、チップマウントランド拡大平面図、Ｂ−Ｂ’線
断面一部拡大図。第６図は本発明による放熱板を示し同
図（ａ）〜（ｅ）は平面図。
右方側面図、ｃ−ｃ’線断面図、正面図、下面図。
第７図は放熱板の面付は図。
１・・・放熱板、２・・・取付穴、６・・・整形された
り−ドフレーム、４・・・モールド樹脂、５・・・放熱
板外周の両面潰し部、６・・・半導体を搭載するための
エリア、７・・・チップマウントランド、８・・・半導
体素子、１４・・・帯状銅箔パターン、２０・・・絶縁
層。
特許出願人 東京芝浦電気株式会社
代理人 弁理士 諸田英二
□
第１図
第２図
ＯＪ ｒｏ−
ｒつ へ
匡３FIG. 1 is an external view of an insulated semiconductor device with a resin-sealed heat sink, which is the same as the conventional one and the one according to the present invention. Figures 1 and 2 are a plan view and a front view, respectively. Figure 2 is a diagram of the internal structure of the semiconductor device shown in Figure 1, with the molding resin removed. A cross-sectional view, a front view, and a bottom view. FIG. 5 shows a lead frame that is the same as the conventional one and the one according to the present invention, and FIG. . FIG. 6 shows a heat sink according to the present invention, and FIGS. 6(a) to 6(e) are plan views. A right side view, a sectional view taken along the line c-c', a front view, and a bottom view. Figure 7 shows the mounting of the heat sink. DESCRIPTION OF SYMBOLS 1... Heat sink, 2... Mounting hole, 6... Shaped frame, 4... Molded resin, 5... Double-sided flattened portion on the outer periphery of heat sink, 6... Semiconductor Area for mounting, 7... Chip mounting land, 8... Semiconductor element, 14... Band-shaped copper foil pattern, 20... Insulating layer. Patent applicant Tokyo Shibaura Electric Co., Ltd. Agent Patent attorney Eiji Morota □ Figure 1 Figure 2
Claims (1)
してなる絶縁基板を用いた放熱板があり、かつ該銅箔に
は少なくとも一つの半導体素子を搭載するためのエリア
を有するパター／が形成された該放熱板を用い、半導体
素子を搭載し、樹脂封止してなる半導体装置において、
該銅箔上に帯状の銅箔パター；／を形成し、該帯状の銅
箔パターンと放熱板外周の両面又は片面の潰し部とによ
り、上記半導体素子を搭載するため、エリア周囲を、包
囲した放熱板を使用したことを特徴とする樹脂封止放熱
板付絶縁形半導体装置。 ２ 半導体素子を搭載するのに、少くとも一つの半導体
素子を搭載するためのチップマウントランドを設けた銅
系又は鉄系リードフレームの該チップマウントランドを
介して放熱板の該エリアに半導体素子を固着してなる、
特許請求の範囲第１項記載の半導体装置。 ６ 放熱板の該エリアに半導体素子を搭載し直接該エリ
アに固着してなる特許請求の範囲第１項記載の半導体装
置。[Claims] 1. There is a heat dissipation plate using an insulating substrate formed by interposing an insulator between an aluminum plate or a copper plate and a copper foil, and the copper foil has a heat dissipation plate for mounting at least one semiconductor element. In a semiconductor device in which a semiconductor element is mounted and resin-sealed using the heat sink on which a pattern having an area is formed,
A strip-shaped copper foil pattern is formed on the copper foil, and the strip-shaped copper foil pattern and the crushed portion on both sides or one side of the outer periphery of the heat sink surround the area for mounting the semiconductor element. An insulated semiconductor device with a resin-sealed heat sink, characterized in that it uses a heat sink. 2. When mounting a semiconductor element, the semiconductor element is mounted on the area of the heat sink via the chip mount land of a copper or iron lead frame provided with a chip mount land for mounting at least one semiconductor element. It becomes stuck,
A semiconductor device according to claim 1. 6. The semiconductor device according to claim 1, wherein a semiconductor element is mounted on the area of the heat sink and directly fixed to the area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58127900A JPS6021547A (en) | 1983-07-15 | 1983-07-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58127900A JPS6021547A (en) | 1983-07-15 | 1983-07-15 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6021547A true JPS6021547A (en) | 1985-02-02 |
Family
ID=14971437
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58127900A Pending JPS6021547A (en) | 1983-07-15 | 1983-07-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6021547A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60245544A (en) * | 1984-05-22 | 1985-12-05 | 新日本製鐵株式会社 | Steel pipe coated with polypropylene |
-
1983
- 1983-07-15 JP JP58127900A patent/JPS6021547A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60245544A (en) * | 1984-05-22 | 1985-12-05 | 新日本製鐵株式会社 | Steel pipe coated with polypropylene |
| JPH0136784B2 (en) * | 1984-05-22 | 1989-08-02 | Shinnippon Seitetsu Kk |
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