JPS60209867A - Common bus control system - Google Patents

Abstract

PURPOSE:To operate a CPU efficiently by constituting a system so that only the bus control circuit part of one processor is operated and the other processors use a common bus under the control of this operated bus control circuit part. CONSTITUTION:When a CPU20 is used as a main processor and CPU 21 is used as a subprocessor, a bus control operation inhibiting control signal is generated from a bus control circuit 22 at a power-on time and is inputted to a bus control operation inhibiting control circuit 25 connected to the CPU21, and a bus control part 23 connected to the CPU21 is set to the operation inhibiting state. hereafter, the CPU21 transmits a bus request signal to the bus control circuit 22, which is connected to the CPU20, through a bus request transmitting/permission receiving circuit 27 connected to the CPU21 itself and receives a bus use permission signal from this bus control circuit 22. Meanwhile, the control operation is executed between the CPU20 and the bus control circuit 22 by the clock synchronizing system.

Description

TECHNICAL FIELD OF THE INVENTION The invention relates to a common path control scheme in a multiprocessor system in which multiple processors are connected to the same common bus.

(b) Prior art and problems Conventionally, when configuring a multiprocessor system by connecting multiple processors on a common path, one CPU (
Do you attach a bus control circuit only to the main processor to perform all bus management, or do you add a bus control circuit externally that controls the whole thing? They have adopted a method of making money and managing the buses. In this case, in the former method, the CPU 11111, which does not have a bus control circuit, always has the disadvantage that the operating efficiency decreases, and in the latter method, if a failure occurs in the central bus control circuit, the entire system There are disadvantages that the CPU goes down and, as will be described later, that the operating efficiency of each CPU is not good.

ff11 is a system configuration diagram of a conventional example that has a bus control circuit unit externally controlling the whole. 9
10 to 13 are bus permission signals (AVJ lines). In FIG. 1, - data bus lines, address bus lines, etc. are completely omitted from illustration.

In the configuration example shown in FIG. It sends the bus usage number 8'1 (AV) to the device that issued the request and allows it to use the bus. In addition, if several such requests occur at the same time, the bus will be used for one rainbow according to the priority order of F'i feet.
1 = issue (AV)k is sent.

Figure 2 is a diagram showing the bus control timing in the case of the conventional example shown in Figure 1, where CPIJI (M-AIN) is the operating period of the main processor, CPU2 (SUB)
During the operation period of the sub processor, BS-RQMAIN is the bus request signal from the main processor, BSRQSU
Bus request number 1d from BrC sub-side processor, BSA
VMAIN indicates the bus usage permission oJ to the main processor, BSAV SUB indicates the sub 011170, the bus usage needle signal to the main processor, the part J indicated by the broken line in the figure, and the wait state period of each processor. . As is clear from Fig. 2, it cannot be said that the efficiency of each processor is necessarily good. The purpose is to operate the system well and to prevent the entire system from going down even if there is a failure in the bus control Lglj path during operation.

B) Structure of the Invention In order to achieve the above object, in a multiprocessor system of a common bus type in which a non-exploded aAμ, 0 number 10 setter and equipment controlled by the processor are connected to the same common path, each of the processors is , a bus control circuit section,
The bus control circuit s1&: a circuit section whose operation is prohibited;
Sends a bus use request signal to the path control M circuit section of the other processor, and @bus control I of the other processor! l! 1
Sends a bus request to receive a bus permission signal from the road section/
A permission receiving circuit is provided, and only one of the processor's bus control circuits is in an operating state, and other processors are made to use a common bus under the control of one of the bus control circuits in the operating state. What you accomplished is expressed as a percentage.

09 Examples of the invention FIG. 3 shows a multi-groove 7 according to one embodiment of the invention.

20.21 is a processor (CPU), 22.23 is a bus control circuit, and 24.
．． 25 is a bus control operation prohibition control circuit, 26.27 is a bus request sending/permission receiving N path, 28 is a DMA circuit, 29,3
01CCPf tower 1tis Plate IJ/to board, 31 is the 4m number. In FIG. 3, the CPU 20. CPU21. DMA circuit 2
Although only 8 is shown in the figure, there are generally n numbers, and between the path control circuit M22, 23, the bus request signal line group 31, and the bus use permission signal line group 32, there are n-1 signals each. Note that in FIG. 3, illustrations of data bus lines, address bus lines, etc. are omitted.

The operation in Figure 3 is as follows.0 First, when the power to each part is turned on, a bus control operation prohibition control signal is sent from the bus control circuit connected to the CPU that should operate as the main CPU to other CPVs. The signal is input to the connected bus control operation prohibition control circuit. For example, CPU20
t'' main processor and C-PU21t-subprocessor, the bus control circuit 22 generates a bus control operation stop control signal BCINH2, and the subprocessor CP
The signal is input to the bus control operation prohibition control circuit 25 connected to U21.

As a result, the bus control circuit 23 connected to the sub-processor CPU 21 is prohibited from operating. In other words, within the system, bus system #! Only the path control circuit 22 connected to the main processor CPυ20 is required to perform the It.

Thereafter, the sub-processor CPU 21 connects to the bus control circuit 2 connected to the main processor CPU 20 via the bus request sending/grant receiving N path 27 connected to its own gross processor.
2, the bus request Gl@t' is sent, and the bus control circuit 2
In other words, regarding the sub-processor CPU 21, the same control form miv as in the conventional system is adopted. -10,000, the main processor CPU20 is
It is directly connected to the bus control circuit 22, and control operations are executed between the main processor 20 and the bus control circuit 22 in a clock synchronous manner. In other words, between Ga Nagisa, requests/
Since it does not depend on the response method, it is immediately determined and processed whether or not the bus can be used ◇ ff14 Figure shows the bus control timing of the embodiment. The operation period, CPU2 (SYB) is the operation period of the sub-side processor, BSRQ SUB is the bus request signal from the sub-side processor, BSAVSUBIJ is the bus usage information for the sub-side processor. 1, which is the wait state period of the grosser, and the 21st worst conventional 1j
As is clear from the comparison, the CPU i+JI) operation rate 1-1. It has been improved to thick iQ.

Although not shown in Figure 3, there is a management device that manages the entire system 1c, and if a failure occurs in the bus control circuit that is in operation, the bus control circuit connected to other CPUs Control is performed before the circuit becomes operational.

(f) Effect of invention The following effects can be obtained by non-invention.

■ The required CPU can be operated efficiently.

■ Since each CPU unit can operate independently, the degree of freedom in system configuration is increased.

(2) Failure of one bus control circuit does not cause the entire system to go down. That is, when a unit bus control circuit fails, the bus control circuit of another unit can be used.

Furthermore, even if either the bus control circuit or the bus request sending/fraudulent receiving circuit fails within t units, operation is possible by using the other means.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram of a conventional example, FIG. 2 is a diagram showing bus control timing of a conventional example, FIG. 3 is a block diagram of a multiprocessor system according to an embodiment of the present invention, and FIG. FIG. 3 is a diagram that does not show bus control timing. In FIG. 3, 20; 21 are Brosets, 22.23 are bus control circuits, 24.25 are pass il+control operation inhibition control circuits,
26 In H27, a bus request was issued/a total of iIJ reception circuits were used. Humiliation 1 figure

Claims (1)

[Claims] In a common path multiprocessor system in which multiple processors and devices controlled by the processors are connected to the same common path, each of the processors has a bus control section and a path control circuit section that controls all operations. Sends a bus request signal to the bus control circuit section of the other processor and the bus control circuit section of the other processor, and receives the bus use Ii'F town 1n signal from the bus control circuit section of the other processor. All the f-receiver circuit units are provided, and only one of the 10 processors' bus control circuit unit is in an operating state, and the other processors are set to one of the bus control circuit units in the operating state.
A common bus control system characterized in that it is configured to use a common path vi- under the control of