JPS60208874A - Manufacture of josephson junction element - Google Patents

Manufacture of josephson junction element

Info

Publication number
JPS60208874A
JPS60208874A JP59066301A JP6630184A JPS60208874A JP S60208874 A JPS60208874 A JP S60208874A JP 59066301 A JP59066301 A JP 59066301A JP 6630184 A JP6630184 A JP 6630184A JP S60208874 A JPS60208874 A JP S60208874A
Authority
JP
Japan
Prior art keywords
tunnel barrier
electrode
substrate
etching
superconducting electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59066301A
Other languages
Japanese (ja)
Inventor
Hisanao Tsuge
拓植 久尚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59066301A priority Critical patent/JPS60208874A/en
Publication of JPS60208874A publication Critical patent/JPS60208874A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • H10N60/0912Manufacture or treatment of Josephson-effect devices

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE:To form a tunnel barrier part having high dimensional accuracy, by performing the anisotropic etching of the mask of the tunnel barrier part, and completely etching the part other than the mask by ion beam, which is projected at an angle of 30-50 deg. with respect to the direction normal to a substrate. CONSTITUTION:On an insulating substrate 11, a first superconductive electrode 12 of Nb, a tunnel barrier layer 15 and a second superconductive electrode 21 of Pb, i.e. three-layer films, are formed. A resist mask 22 is formed at a place, which is to become the tunnel barrier part on the second superconductive electrode 21. Thereafter, the second superconductive electrode 21 is etched by ions by using an obliquely inputting ion beam at an angle of 30-50 deg. with respect to the direction normal to the substrate 11. Then an insulator layer 14 comprising SiO and the like is deposited on the entire surface of the substrate by a film forming method having excellent directivity. The resist mask 22 is lifted off and a pattern is formed. Thereafter, a third superconductive electrode 23 is formed by the same way for the first superconductive electrode 12 and the second superconductive electrode 21.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はジョセフソン接合素子の製造方法に関し、特に
トンネル障壁型のジョセフソン接合素子の製造方法に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a Josephson junction device, and more particularly to a method for manufacturing a tunnel barrier type Josephson junction device.

(従来技術とその問題点) 一般に、ジョセフソン接合素子から構成される論理回路
や記憶回路には、接合特性が、優れ、この特性の各素子
間でのばらつきが小さり、シかも熱サイクルによる特性
劣化の小さい素子が要求される。これら優れた接合特性
と高信頼性という両方の集積化条件を満たす素子として
、第1の超伝導体電極にニオブ(Nb )またはNb化
合物を。
(Prior art and its problems) In general, logic circuits and memory circuits composed of Josephson junction elements have excellent junction characteristics, and variations in these characteristics between elements are small, and they are easily affected by thermal cycles. Elements with minimal characteristic deterioration are required. Niobium (Nb) or a Nb compound is used for the first superconductor electrode as a device that satisfies both the integration requirements of excellent bonding properties and high reliability.

第2の超伝導体電極に鉛(pb)またはPb合金を用い
たものが注目されている。しかしながら。
Those using lead (pb) or a Pb alloy for the second superconductor electrode are attracting attention. however.

このPb系材料は化学的に不安定であるため、従来この
パターニング方法としてはリフトオフ法に限られていた
Since this Pb-based material is chemically unstable, conventional patterning methods have been limited to the lift-off method.

この従来例として、R,F*Broom等によって19
80年10月に米国雑誌” IEEE Transac
t−ions on Electron Device
s ”の第ED−27巻第10号1998〜2008頁
に発表された論文などがある。この論文による方法を第
1図(a)〜げ)の断面図を用いて工程順に説明する。
As a conventional example of this, 19
In October 1980, American magazine “IEEE Transac
t-ions on Electron Device
There is a paper published in ED-27, No. 10, pages 1998-2008 of ``S'', Vol.

まず、第1図(alに示すように、絶縁体基板あるいは
表面に絶縁体層を有する基板11上に、蒸着法やスパッ
タ法によりNbからなる第1の超伝導体電極12を形成
する。mlの超伝導体電極12のバターニングは通常の
ホトレジスト工程を用いた工、チング法やリフトオフ法
で行なう。次に第1図(b)に示すように第1の超伝導
体電極12上のトンネル障壁部となる部分にアンダーカ
ット形状のレジストマスク13を形成し、11図(C)
に示すように基板表面に蒸着法などの指向性の良い成膜
法で一酸化ケイ素(8i0)、二酸化ケイ素(Sin、
)等からなる絶縁体層14を被着し、引続きリフトオン
すると第1図(山に示すような開口部をもつトンネル障
壁部が形成される。アンダーカット形状のレジストマス
ク13は通常のホトレジスト工程に加え、露光前または
露光後にクロロベンゼンやブロモベンゼンなどの有機溶
剤に浸すことによって得られる。次に、第1図(e)に
示2すように熱酸化法あるいはプラズマ酸化法でトンネ
ル障壁部に数1OA厚さのトンネル障壁層15を形成す
る。この後、第1図(f)に示すように、蒸着法および
リフトオフ法で第2の超伝導体電極16を形成する。
First, as shown in FIG. 1 (al), a first superconductor electrode 12 made of Nb is formed on an insulating substrate or a substrate 11 having an insulating layer on its surface by vapor deposition or sputtering. The patterning of the first superconductor electrode 12 is carried out using a conventional photoresist process, a ching method, or a lift-off method.Next, as shown in FIG. A resist mask 13 with an undercut shape is formed in the part that will become the barrier part, and as shown in FIG. 11(C).
As shown in Figure 2, silicon monoxide (8i0), silicon dioxide (Sin,
), etc., and then lift-on to form a tunnel barrier section with an opening as shown in FIG. In addition, it can be obtained by immersing it in an organic solvent such as chlorobenzene or bromobenzene before or after exposure.Next, as shown in Figure 1(e), several layers are applied to the tunnel barrier section by thermal oxidation method or plasma oxidation method. A tunnel barrier layer 15 having a thickness of 1 OA is formed.Thereafter, as shown in FIG. 1(f), a second superconductor electrode 16 is formed by a vapor deposition method and a lift-off method.

この製造方法は、トンネル障壁部の形成にアンダーカッ
ト形状のレジストマスク13を必要とするが、このマス
クの形状はレジストのプリベーク条件や有機溶剤の液温
、ディ、プ時間などの影響Qけやすい。特に、トンネル
障壁部の有効面積を規定するレジストマスク13下部の
寸法を精度よ(得ることは非常に難しい。また、トンネ
ル障壁部のスパッタクリーニングやプラズマ酸化時に絶
縁体層14からのスパッタ物によりトンネル障壁部が汚
染されると伝5欠点もあった。
This manufacturing method requires an undercut-shaped resist mask 13 to form the tunnel barrier, but the shape of this mask is easily influenced by resist pre-baking conditions, organic solvent temperature, dipping time, etc. . In particular, it is very difficult to accurately adjust the dimensions of the lower part of the resist mask 13, which defines the effective area of the tunnel barrier.Also, during sputter cleaning or plasma oxidation of the tunnel barrier, sputtered materials from the insulator layer 14 may There were also five drawbacks when the barrier became contaminated.

(発明の目的) 本発明の目的は、このような従来の欠点を取除キ、オー
バーエツチングがなく、寸法精度よくトンネル障壁部を
形成できるジョセフソン接合素子の製造方法を提供する
ことにある。
(Objects of the Invention) It is an object of the present invention to provide a method for manufacturing a Josephson junction element that eliminates such conventional drawbacks, eliminates overetching, and allows formation of a tunnel barrier portion with high dimensional accuracy.

(発明の構成) 本発明のジョセフソン接合素子の製造方法の構成は、基
板上にNbまたはNb化合物からなる所定パターンの第
1の超電導電極、この第1の超電導電極上にトンネル障
壁層、このトンネル障壁層上にPbまたはPb合金から
なる第2の超電導電極を連続して形成する第1の工程と
、前記第2の超電導電極上のトンネル障壁層となる個所
にエツチングマスクを形成しこのマスク以外の個所の第
2の超電導電極部分を前記基板の法線方向に対して30
〜50度の傾め入射するイオンビームにより完全にイオ
ンエツチングする第2の工程と、前記第2の超電導電極
の被エツチング部と前記パターン以外の基板面とを埋め
るように絶縁体層を被着しその後前記エツチングマスク
を除く第3の工程と、前記第2の超電導電極と接触する
個所を含んで前記絶縁体層上に第3の超電導電極を被着
する第4の工程とを備えることを特徴とする。
(Structure of the Invention) The structure of the method for manufacturing a Josephson junction element of the present invention is such that a first superconducting electrode of a predetermined pattern made of Nb or a Nb compound is formed on a substrate, a tunnel barrier layer is formed on the first superconducting electrode, and a tunnel barrier layer is formed on the first superconducting electrode. A first step of successively forming a second superconducting electrode made of Pb or a Pb alloy on the tunnel barrier layer, and forming an etching mask at a location on the second superconducting electrode that will become the tunnel barrier layer. The second superconducting electrode portion at a location other than 30° relative to the normal direction of the substrate.
A second step of completely ion etching with an ion beam incident at an angle of ~50 degrees, and depositing an insulating layer so as to fill the etched portion of the second superconducting electrode and the surface of the substrate other than the pattern. and then a third step of removing the etching mask, and a fourth step of depositing a third superconducting electrode on the insulator layer including a portion in contact with the second superconducting electrode. Features.

(実施例) 以下本発明を図面により詳細に説明する。(Example) The present invention will be explained in detail below with reference to the drawings.

第2図(a)〜(ωは本発明の実施例を工程順に説明す
る断面図である。まず、第2図(a)に示すように、絶
縁体基板あるいは表面に絶縁体層を有する基板ll上に
、NbまたはNb化合物からなる第1の超電導電極12
、トンネル障壁層15.Pbまたはpb金合金らなる第
2の超伝導体電極21の3層膜を形成する。これら第1
および第2の超電導体電極12.21は蒸着法またはス
パッタ法で形成する。また、トンネル障壁層15は第1
の超伝導体電極12表面を熱やプラズマにより酸化する
か絶縁体膜、半導体膜を被着して形成する。これら3層
膜11i5,2tのパターニングは通常のレジスト工程
を用いたエツチング法やリフト、オフ法によって行う。
FIGS. 2(a) to ω are cross-sectional views explaining the embodiments of the present invention in the order of steps. First, as shown in FIG. 2(a), an insulating substrate or a substrate having an insulating layer on the surface ll, a first superconducting electrode 12 made of Nb or a Nb compound
, tunnel barrier layer 15. A three-layer film of the second superconductor electrode 21 made of Pb or a Pb gold alloy is formed. These first
And the second superconductor electrode 12.21 is formed by a vapor deposition method or a sputtering method. Further, the tunnel barrier layer 15 is
The superconductor electrode 12 is formed by oxidizing the surface of the superconductor electrode 12 by heat or plasma, or by depositing an insulating film or a semiconductor film. Patterning of these three-layer films 11i5 and 2t is performed by an etching method using a normal resist process or a lift-off method.

次に、第2図Φ)に示すように第2の超伝導体電極21
上のトンネル障壁部となる場所にレジストマスク22を
形成した後、第2図(C1および(d)に示すように、
基板11の法線方向に対して30〜50度の斜め入射イ
オンビームを用いて第2の超伝導体電極21をイオンエ
ツチングする。第2図(C1に示すように、ジャストエ
ツチングの状態では、第2の超伝導体電極21のすそが
広がっているが、はぼ同一時間だけオーバーエツチング
することによって第2の超伝導体電極21は、第2図(
d)に示すように、矩形状のパターンとなる。
Next, as shown in FIG. 2 Φ), the second superconductor electrode 21
After forming a resist mask 22 at a location that will become the upper tunnel barrier section, as shown in FIG. 2 (C1 and (d)),
The second superconductor electrode 21 is ion-etched using an ion beam incident obliquely at an angle of 30 to 50 degrees with respect to the normal direction of the substrate 11 . As shown in FIG. 2 (C1), in the just-etched state, the base of the second superconductor electrode 21 is widened, but by over-etching for approximately the same amount of time, the second superconductor electrode 21 is widened. is shown in Figure 2 (
As shown in d), it becomes a rectangular pattern.

次に、第2図(elに示すように、基板全面に蒸着法や
イオンビームデポジション法などの指向性の良い成膜法
により8i0.SiO□等でなる絶縁体層14を被着し
、レジストマスク22をリフトオンして第2図(f)の
ようなパターンを形成する。この後第2図(2)に示す
ように、第1の超伝導体電極12゜第2の超伝導体電極
21と同様な成膜法および加工法により、第3の超伝導
体電極23を形成する。
Next, as shown in FIG. 2 (el), an insulating layer 14 made of 8i0.SiO□ or the like is deposited on the entire surface of the substrate by a film forming method with good directionality such as vapor deposition or ion beam deposition. The resist mask 22 is lifted on to form a pattern as shown in FIG. 2(f).After this, as shown in FIG. A third superconductor electrode 23 is formed using the same film forming method and processing method as in 21.

本実施例のよ5に、斜め入射エツチングを用いる場合に
は、第2図(C)に示すように、第2の超伝導体電極2
1とレジストパターン22のシャドウ効果によって第2
の超伝導体電極21にすそを生じるが、これはジャスト
エツチング時間とほぼ同一時間だけオーバーエツチング
することによって除去することができる。この際に基板
11や第1の超伝導体電極12のエツチングが懸念され
るがこの構成の素子では大きな選択比が得られるため問
題はない。また、エツチング後の第2の超伝導体電極1
2.レジストパターン22の矩形性が優れているため、
引続くリフトオフを容易に精度よく行なうことができる
When using oblique incidence etching as in this embodiment, as shown in FIG. 2(C), the second superconductor electrode 2
1 and the shadow effect of the resist pattern 22.
This produces a skirt on the superconductor electrode 21, which can be removed by overetching for approximately the same time as the just etching time. At this time, there is a concern that the substrate 11 and the first superconductor electrode 12 may be etched, but there is no problem because a large selectivity can be obtained with the element having this configuration. Also, the second superconductor electrode 1 after etching
2. Since the resist pattern 22 has excellent rectangularity,
Subsequent lift-off can be performed easily and accurately.

第3図はpbのイオンビームエツチングにおけるパター
ン幅変化量Δw/bとビーム入射角θとの関係を示す特
性図である。ここで、パターン幅変化量Δw/dはエツ
チング深さdで規格化したレジストマスク幅に対するP
6パターン幅の増加量ΔWであり、ビーム入射角θは、
入射イオンビームが基板の法線方向に対してなす角度で
ある。この図から明らかなように、ビーム入射角θが約
40度でパターン幅変化量Δ−/・dがほとんどない加
工物パターンを形成することができる。PbおよびPb
合金に最適なビーム入射角θは材料に多少依存するが、
30〜50度と考えられる。
FIG. 3 is a characteristic diagram showing the relationship between pattern width change amount Δw/b and beam incident angle θ in pb ion beam etching. Here, the pattern width change amount Δw/d is P with respect to the resist mask width normalized by the etching depth d.
6 The increase in pattern width is ΔW, and the beam incidence angle θ is:
This is the angle that the incident ion beam makes with respect to the normal direction of the substrate. As is clear from this figure, it is possible to form a workpiece pattern with a beam incident angle θ of about 40 degrees and almost no pattern width variation Δ−/·d. Pb and Pb
The optimal beam incidence angle θ for alloys depends somewhat on the material, but
It is thought to be between 30 and 50 degrees.

この製造方法では、トンネル障壁部の形成に再現性の良
い矩形レジストマスクが利用できると、イオンエツチン
グ法によりレジストマスク22からM2の超伝導体電極
21への高精度のパターン転写が可能であることから、
従来のリフトオフ法に用いた方法に比ベトンネル障壁部
の寸法を制御し易い。
In this manufacturing method, if a rectangular resist mask with good reproducibility can be used to form the tunnel barrier portion, it is possible to transfer a pattern with high precision from the resist mask 22 to the M2 superconductor electrode 21 using the ion etching method. from,
It is easier to control the dimensions of the tunnel barrier compared to methods used in conventional lift-off methods.

(具体例) 次に本発明の詳細な説明する。(Concrete example) Next, the present invention will be explained in detail.

表面が熱酸化5in2で被覆されたシリコン(Si)基
板(11)上に、電子ビーム蒸着法により基板温度30
0CでNb膜(12)を厚さ2000A被着する。引続
き、同一装置内で2%の酸素(02)を含むアルゴン(
Ar)−0を混合ガスを用いて、全圧力lXl0 To
rr、カソード電圧−170V−?’Nb膜表面を10
分間プラズマ酸化し、20〜30Xの酸化ニオブ(N 
b20g )膜(15)を形成する。
A silicon (Si) substrate (11) whose surface is coated with thermal oxidation 5in2 is heated to a substrate temperature of 30% by electron beam evaporation.
A Nb film (12) with a thickness of 2000A is deposited at 0C. Subsequently, in the same apparatus, argon containing 2% oxygen (02) (
Using a mixed gas of Ar)-0, the total pressure lXl0 To
rr, cathode voltage -170V-? 'Nb film surface 10
Plasma oxidize for 20-30X niobium oxide (N
b20g) Form a film (15).

この後、連続して室温でPb膜(21)を厚さ2000
λ蒸着する。この膜上にポジ型ホトレジスト(シラプレ
ー社製AZ1350J)を用いた通常のホトレジスト工
程で膜厚1,5μmのレジストマスク22を形成した後
、平行平板型のスパッタエツチング装置を用いて、Ar
、フロン13 (CF、)それぞれpb(21)、Nb
/Nb2O,(15)を連続エツチングして第1の超伝
導体電極パターンを形成する。
After this, the Pb film (21) was continuously deposited at room temperature to a thickness of 2000 mm.
Deposit λ. After forming a resist mask 22 with a film thickness of 1.5 μm on this film using a normal photoresist process using a positive type photoresist (AZ1350J manufactured by Silaplay Co., Ltd.), Argon etching was performed using a parallel plate type sputter etching device.
, Freon 13 (CF,)pb(21), Nb respectively
/Nb2O, (15) is continuously etched to form a first superconductor electrode pattern.

次に前記3層膜12s15s21上のトンネル障壁部と
なる場所に直径1.5μm、膜厚5000Aのレジスト
マスクをパターニングした後、40度のビーム入射角を
用いたイオンエツチング法でpb膜(21)を完全に除
去し、第2の超伝導体電極パターンを形成する。、この
エツチング条件はAr圧力2X] 0 ’Torr 、
加速電圧500V、電流密度0、 g m A / c
n2である。次に、基板11上に2000λの5in(
14)を蒸着し、レジストマスク22をアセトン中の超
音波洗浄でり7トオフする。基板表面をArでスパッタ
クリーニングした後、第2の超伝導体電極パターン形成
と同様な方法で3000AのPb膜でなる第3の超伝導
体電極23を形成する。
Next, after patterning a resist mask with a diameter of 1.5 μm and a film thickness of 5000 A at the location on the three-layer film 12s15s21 that will become the tunnel barrier, the PB film (21) is etched using an ion etching method using a beam incidence angle of 40 degrees. is completely removed to form a second superconductor electrode pattern. , this etching condition is Ar pressure 2X] 0'Torr,
Accelerating voltage 500V, current density 0, g m A/c
It is n2. Next, on the substrate 11, a 5 inch (2000λ)
14) is deposited, and the resist mask 22 is removed by ultrasonic cleaning in acetone. After sputter cleaning the substrate surface with Ar, a third superconductor electrode 23 made of a 3000A Pb film is formed in the same manner as in forming the second superconductor electrode pattern.

この製造方法では、第2の超伝導体重>21のパル−二
ンfの9、AZ1350JKNするPbのエツチング速
度比は5と大ぎく、しかも[24度の異方性エツチング
が可能なため、レジストマスクに対するトンネル障壁部
のパターン寸法変化をほとんど生じない。また、Pbは
泥1の超伝導体電極であるNb、下地絶縁1i) S 
t 02に対してもそれぞれ7〜8,4〜5と大きなエ
ツチング速庇比をもつだめ、Pbの選択エツチングが可
能である。
In this manufacturing method, the etching rate ratio of Pb to AZ1350JKN is as large as 5 to 9 of the second superconductor f with a weight of >21. There is almost no change in pattern dimensions of the tunnel barrier section with respect to the mask. In addition, Pb is the superconductor electrode of Mud 1, Nb is the base insulation 1i) S
Selective etching of Pb is possible because they have large etching speed ratios of 7-8 and 4-5 for t02, respectively.

なお、この具体例では、諏lの超伝導体を極12として
Nbを、第2および第3の超伝導体電極21tとしてP
bを用いた場合について説明したが、それぞれN b化
合物、Pb合金でも同様な結果が得られる。ただし、蕗
3の超伝導体電極23には。
In addition, in this specific example, Nb is used as the pole 12 of the superconductor 12, and P is used as the second and third superconductor electrodes 21t.
Although the case where B is used has been described, similar results can be obtained with N b compounds and Pb alloys, respectively. However, for the superconductor electrode 23 of the butterfly 3.

NbあるいはN、b化合物を用いることもできる。Nb or N,b compounds can also be used.

また、トンネル障壁層15には第1の超伝導体電極12
の表面の酸化層以外に、被着により形成した絶縁体層、
トンネル障壁層を酸化する場合には金属層、半導体層も
適用できる。さらに、トンネル障壁部を形成するための
マスクとしてAZ1350Jを使用したが、他の有機レ
ジスト、無機レジストなとも用いることができる。
Further, the tunnel barrier layer 15 is provided with a first superconductor electrode 12.
In addition to the oxide layer on the surface, an insulator layer formed by deposition,
When oxidizing the tunnel barrier layer, metal layers and semiconductor layers can also be used. Furthermore, although AZ1350J was used as a mask for forming the tunnel barrier section, other organic resists or inorganic resists may also be used.

(発明の効果) 以上説明したように、本発明によれば、トンネル障壁部
を優れた異方性エツチング法で形成していることから、
高寸法精度のトンネル障壁部を有するジョセフソン接合
素子を製造することができる。
(Effects of the Invention) As explained above, according to the present invention, since the tunnel barrier portion is formed by an excellent anisotropic etching method,
A Josephson junction device having a tunnel barrier portion with high dimensional accuracy can be manufactured.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(f)は従来のジョセフソン接合素子の
製造方法を工程順に説、明する断面図、第2図(al〜
(ロ)は本発明の一実施例を工程順に説明する素子の断
面図、第3図はPbのイオンビームエツチングにおける
パターン幅変化量Δw/d(ΔW:Vシストマスクに対
するパターン幅増加量、d:エッチング深さ)とビーム
入射角θとの関係を示すグラフである。図において 11・・・・・・基板、12・・・・・・第1の超伝導
体電極、13.22・・・・・・レジストマスク、14
・・・・・・絶縁体層、15・・・・・・トンネル障壁
層、16,21・・・・・・第2の超伝導体電極、23
・・・・・・第3の超伝導体電極である。 ″、−一−ノ′ 石/図
FIGS. 1(a) to 1(f) are cross-sectional views illustrating a conventional method for manufacturing a Josephson junction device in the order of steps, and FIGS.
(B) is a cross-sectional view of an element explaining one embodiment of the present invention in the order of steps, and FIG. : etching depth) and beam incident angle θ. In the figure, 11...Substrate, 12...First superconductor electrode, 13.22...Resist mask, 14
...Insulator layer, 15...Tunnel barrier layer, 16, 21...Second superconductor electrode, 23
...This is the third superconductor electrode. ″、−1−ノ′ Stone/Figure

Claims (1)

【特許請求の範囲】[Claims] 基板上にNbまたはNb化合物からなる所定パターンの
第1の超電導電極、この第1の超電導電極上にトンネル
障壁層、このトンネル障壁層上にpbまたはPb合金か
らなる第2の超電導電極を連続して形成する第1の工程
と、前記第2の超電導電極上のトンネル障壁部となる個
所にエツチングマスクを形成しこのマスク以外の個所の
第2の超電導電極部分を前記基板の法線方向に対して3
0〜50度の傾め入射したイオンビームにより完全にイ
オンエツチングする第2の工程と、前記第2の超電導電
極の被エツチング部と前記パターン以外の基板面とを埋
めるように絶縁体層を被着しその後前記エツチングマス
クを除く第3の工程と、前記第2の超電導電極と接触す
る個所を含んで前記絶縁体層上に第3の超電導電極を被
着する第4の工程とを備えることを特徴とするジョセフ
ソン接合素子の製造方法。
A first superconducting electrode of a predetermined pattern made of Nb or a Nb compound is formed on a substrate, a tunnel barrier layer is formed on this first superconducting electrode, and a second superconducting electrode made of Pb or a Pb alloy is continuously formed on this tunnel barrier layer. a first step of forming the second superconducting electrode, and forming an etching mask at a portion of the second superconducting electrode that will become the tunnel barrier portion, and etching the second superconducting electrode portion other than the mask with respect to the normal direction of the substrate; te3
A second step of completely ion etching with an ion beam incident at an angle of 0 to 50 degrees, and covering the insulating layer so as to fill the etched portion of the second superconducting electrode and the surface of the substrate other than the pattern. and a fourth step of depositing a third superconducting electrode on the insulating layer including a portion that contacts the second superconducting electrode. A method for manufacturing a Josephson junction element characterized by:
JP59066301A 1984-04-03 1984-04-03 Manufacture of josephson junction element Pending JPS60208874A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59066301A JPS60208874A (en) 1984-04-03 1984-04-03 Manufacture of josephson junction element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59066301A JPS60208874A (en) 1984-04-03 1984-04-03 Manufacture of josephson junction element

Publications (1)

Publication Number Publication Date
JPS60208874A true JPS60208874A (en) 1985-10-21

Family

ID=13311846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59066301A Pending JPS60208874A (en) 1984-04-03 1984-04-03 Manufacture of josephson junction element

Country Status (1)

Country Link
JP (1) JPS60208874A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3803511A1 (en) * 1987-03-24 1988-10-06 Agency Ind Science Techn METHOD FOR PRODUCING DEVICES WITH JOSEPHSON TRANSITION

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3803511A1 (en) * 1987-03-24 1988-10-06 Agency Ind Science Techn METHOD FOR PRODUCING DEVICES WITH JOSEPHSON TRANSITION
DE3803511C2 (en) * 1987-03-24 1992-02-13 The Agency Of Industrial Science And Technology, Tokio/Tokyo, Jp

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