JPH0334237B2 - - Google Patents
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- Publication number
- JPH0334237B2 JPH0334237B2 JP61054950A JP5495086A JPH0334237B2 JP H0334237 B2 JPH0334237 B2 JP H0334237B2 JP 61054950 A JP61054950 A JP 61054950A JP 5495086 A JP5495086 A JP 5495086A JP H0334237 B2 JPH0334237 B2 JP H0334237B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- superconductor electrode
- mask
- superconductor
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000002887 superconductor Substances 0.000 claims description 61
- 239000012212 insulator Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 238000007743 anodising Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 239000010955 niobium Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 4
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000010407 anodic oxide Substances 0.000 description 2
- 238000002048 anodisation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- OTRAYOBSWCVTIN-UHFFFAOYSA-N OB(O)O.OB(O)O.OB(O)O.OB(O)O.OB(O)O.N.N.N.N.N.N.N.N.N.N.N.N.N.N.N Chemical compound OB(O)O.OB(O)O.OB(O)O.OB(O)O.OB(O)O.N.N.N.N.N.N.N.N.N.N.N.N.N.N.N OTRAYOBSWCVTIN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 description 1
- AFYPFACVUDMOHA-UHFFFAOYSA-N chlorotrifluoromethane Chemical compound FC(F)(F)Cl AFYPFACVUDMOHA-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 1
- 235000019404 dichlorodifluoromethane Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はトンネル型ジヨセフソン素子の製造方
法に関し、さらに詳しくは集積回路に適した微小
なジヨセフソン素子の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a tunnel-type Josephson device, and more particularly to a method for manufacturing a minute Josephson device suitable for integrated circuits.
（従来の技術）
代表的な従来例として、エイツチ・クローガー
（H.Kroger）らによつて1981年８月にアプライ
ド・フイジツクス・レターズ
（AppliedPhysicsLetters）の第39巻第３号280〜
282頁で発表された論文で提案されている方法が
ある。この方法を第２図ａ〜ｃの断面図を用いて
工程順に説明する。第２図ａに示すように、基板
２１上にニオブ（Nb）でなる第１の超伝導体電
極２２に、トンネル障壁層２３、Nbでなる第２
の超伝導体電極２４の３層膜を連続形成する。第
１の超伝導体電極２２および第２の超伝導体電極
２４は直流マグネトロンスパツタ法で被着する。
トンネル障壁層２３はシリコン−水素（Si−Ｈ）
合金を被着し、熱酸化して形成する。上記３層膜
２２，２３，２４をパターニングして下部配線を
形成した後、第２図ｂに示すように第２の超伝導
体電極２４上の接合部となる場所にホトレジスト
でエツチングマスク２５を形成し、引続き第１お
よび第２の超伝導体電極２２，２４をアノードと
して第２の超伝導体電極２４の露出部分をトンネ
ル障壁層まで陽極酸化し絶縁体層２６を形成す
る。エツチングマスク２５を除去した後、第２の
超伝導体電極２４の露出表面をスパツタクリーニ
ングし、第１および第２の超伝導体電極２２，２
４の場合と同様な成膜法で第３の超伝導体電極２
７を被着し、引続き加工すると第２図ｃに示すよ
うなジヨセフソン素子が得られる。(Prior Art) As a typical conventional example, H. Kroger et al. published Applied Physics Letters Vol. 39, No. 3, 280-280 in August 1981.
There is a method proposed in a paper published on page 282. This method will be explained step by step using cross-sectional views of FIGS. 2a to 2c. As shown in FIG. 2a, a first superconductor electrode 22 made of niobium (Nb) is formed on a substrate 21, a tunnel barrier layer 23 is formed, and a second superconductor electrode 22 made of Nb is disposed on a substrate 21.
A three-layer film of the superconductor electrode 24 is successively formed. The first superconductor electrode 22 and the second superconductor electrode 24 are deposited by direct current magnetron sputtering.
The tunnel barrier layer 23 is silicon-hydrogen (Si-H)
Formed by depositing an alloy and thermally oxidizing it. After patterning the three-layer films 22, 23, and 24 to form the lower wiring, as shown in FIG. Then, using the first and second superconductor electrodes 22 and 24 as anodes, the exposed portion of the second superconductor electrode 24 is anodized to the tunnel barrier layer to form an insulator layer 26. After removing the etching mask 25, the exposed surface of the second superconductor electrode 24 is sputter cleaned, and the first and second superconductor electrodes 22, 2
The third superconductor electrode 2 was formed using the same film-forming method as in case 4.
7 and further processing yields a Josephson element as shown in FIG. 2c.
（発明が解決しようとする問題点）
この方法では、第２図ｂに示した陽極酸化の工
程で、酸化は時間とともに等方的に進行するため
エツチングマスク２５下部の第２の超伝導体電極
２４まで一部酸化される。しかもエツチングマス
ク２５下部への酸化層の侵入幅をサブミクロンオ
ーダーで制御するのは容易ではない。従つて、１
〜2μｍ程度の微小接合寸法のジヨセフソン素子
を数多く配した集積回路を作製する場合には、目
標とするジヨセフソン素子の臨界電流値が得られ
ないという問題や、この値のウエーハ内での均一
性が不充分であるという問題を生じる。(Problems to be Solved by the Invention) In this method, in the anodic oxidation step shown in FIG. Partially oxidized up to 24. Furthermore, it is not easy to control the width of penetration of the oxide layer into the lower part of the etching mask 25 on the order of submicrons. Therefore, 1
When fabricating an integrated circuit with a large number of Josephson devices with micro junction dimensions of ~2 μm, there are problems such as not being able to obtain the target critical current value of the Josephson devices, and the uniformity of this value within the wafer. This gives rise to the problem of insufficiency.
本発明の目的は、このような従来の欠点を取り
除いたジヨセフソン素子の製造方法を提供するこ
とにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a Josephson device that eliminates such conventional drawbacks.
（問題点を解決するための手段）
本発明によれば、基板上に第１の超伝導体電
極、トンネル障壁層、第２の超伝導体電極、陽極
酸化のマスクとなる範囲で充分薄いマスク補助層
を連続形成する工程、前記マスク補助層上の接合
部となる箇所にエツチングマスクを形成し、前記
マスク補助層と第２の超伝導体電極と前記トンネ
ル障壁層をドライエツチング除去する工程、前記
エツチングマスクを除去した後第１絶縁体層を被
着する工程、前記第１の絶縁体層をドライエツチ
ングして接合部の側壁を選択的に前記第１の絶縁
体層で被覆する工程、前記第１の超伝導体電極の
露出表面を陽極酸化して第２の絶縁体層を形成す
る工程、前記マスク補助層を除去した後、前記第
２の超伝導体電極と電気的に接触するように第３
の超伝導体電極を形成する工程を含むことを特徴
とするジヨセフソン素子の製造方法が得られる。(Means for Solving the Problems) According to the present invention, a first superconductor electrode, a tunnel barrier layer, a second superconductor electrode, and a sufficiently thin mask to serve as a mask for anodic oxidation are provided on a substrate. a step of continuously forming an auxiliary layer; a step of forming an etching mask at a location on the mask auxiliary layer that will become a junction, and removing the mask auxiliary layer, the second superconductor electrode, and the tunnel barrier layer by dry etching; depositing a first insulating layer after removing the etching mask; dry etching the first insulating layer to selectively cover sidewalls of the joint with the first insulating layer; anodizing the exposed surface of the first superconductor electrode to form a second insulator layer, making electrical contact with the second superconductor electrode after removing the mask auxiliary layer; Like the third
A method for manufacturing a Josephson device is obtained, which includes the step of forming a superconductor electrode.
（作用）
本発明では、まずマスク補助層、第２の超伝導
体電極、トンネル障壁層を順次ドライエツチング
して接合部の寸法を規定し、次に接合部の側壁を
第１の絶縁体層で被覆保護した後、露出した第１
の超伝導体電極を陽極酸化して第１の超伝導体電
極と第３の超伝導体電極との間の電気絶縁のため
の第２の絶縁体層を形成する。そのため、陽極酸
化の際、従来例のように酸化が接合部まで及ぶと
いう問題がない。その結果、ドライエツチング技
術で規定される高寸法精度の微小接合を備え、こ
の接合寸法の場所的なばらつきの小さいジヨセフ
ソン素子の製造が可能となる。(Function) In the present invention, the mask auxiliary layer, the second superconductor electrode, and the tunnel barrier layer are first dry-etched in order to define the dimensions of the junction, and then the sidewalls of the junction are etched with the first insulator layer. After covering and protecting the exposed first
anodizing the superconductor electrode to form a second insulator layer for electrical isolation between the first superconductor electrode and the third superconductor electrode. Therefore, during anodic oxidation, there is no problem that the oxidation extends to the joints as in the conventional example. As a result, it becomes possible to manufacture a Josephson element that has micro-junctions with high dimensional accuracy defined by dry etching technology and has small local variations in the dimensions of these junctions.
しかも、本発明によれば、陽極酸化の際に第２
の超伝導体電極表面の酸化を防止するマスク補助
層はエツチング耐性を必要とするエツチングマス
クとは独立に材料や膜厚を選択できる。従つて、
マスク補助層の膜厚を陽極酸化のマスクとなる範
囲で充分薄くすれば、接合部側壁を第１の絶縁体
層で被覆する際に、マスク補助層への被覆はほと
んどなく、マスク補助層を除去した後も接合部周
辺に突起のない平坦な上部配線が形成できる。 Moreover, according to the present invention, the second
The material and film thickness of the mask auxiliary layer that prevents oxidation of the superconductor electrode surface can be selected independently of the etching mask that requires etching resistance. Therefore,
If the thickness of the mask auxiliary layer is made thin enough to serve as a mask for anodic oxidation, when the sidewall of the joint part is covered with the first insulator layer, there will be almost no coating on the mask auxiliary layer, and the mask auxiliary layer will not be covered. Even after removal, a flat upper wiring without protrusions can be formed around the joint.
（実施例）
次に本発明を第１図ａ〜ｆの断面図に示す実施
例を参照して詳細に説明する。(Example) Next, the present invention will be described in detail with reference to an example shown in cross-sectional views of FIGS. 1a to 1f.
まず、第１図ａに示すように基板１１上に第１
の超伝導体電極１２、トンネル障壁層１３、第２
の超伝導体電極１４、マスク補助層１５を順次形
成する。第１および第２の超伝導体電極１２，１
４は、共にスパツタ法や電子ビーム蒸着法により
被着したそれぞれ膜厚300nｍ、150nｍのNb膜で
ある。トンネル障壁層１３は、スパツタ法や蒸着
法により被着した膜厚約5nｍのアルミニウム
（Al）膜を純酸素（O2）雰囲気中で熱酸化して形
成する。マスク補助層１５は、スパツタ法やプラ
ズマCVD法により被着した膜厚50nｍの窒化シリ
コン（Si3N4）膜である。 First, as shown in FIG.
superconductor electrode 12, tunnel barrier layer 13, second
A superconductor electrode 14 and a mask auxiliary layer 15 are sequentially formed. First and second superconductor electrodes 12,1
4 are Nb films with a thickness of 300 nm and 150 nm, respectively, deposited by sputtering method or electron beam evaporation method. The tunnel barrier layer 13 is formed by thermally oxidizing an aluminum (Al) film with a thickness of about 5 nm deposited by sputtering or vapor deposition in a pure oxygen (O 2 ) atmosphere. The mask auxiliary layer 15 is a silicon nitride (Si 3 N 4 ) film with a thickness of 50 nm deposited by sputtering or plasma CVD.
上記多層膜のパターニングは通常のフオトリソ
グラフイ工程を用いて、まず、マスク補助層１５
をフロン23（CHF3）などのエツチングガスで、
反対性スパツタエツチングした後、次に第２の超
伝導体電極１４、トンネル障壁層１３、第１の超
伝導体電極１２をフロン12（CCl2F2）やフロン13
（CF4）で反応性スパツタエツチングする。 The multilayer film is patterned using a normal photolithography process. First, the mask auxiliary layer 15 is
with an etching gas such as Freon 23 (CHF 3 ).
After anti-sputter etching, the second superconductor electrode 14, tunnel barrier layer 13, and first superconductor electrode 12 are coated with fluorocarbon 12 (CCl 2 F 2 ) or fluorocarbon 13.
(CF 4 ) reactive sputter etching.
次に、第１図ｂに示すようにマスク補助層１５
上の接合部となる場所にエツチングマスク１６を
形成した後、上記多層膜のエツチングと同様にマ
スク補助層１５、第２の超伝導体電極１４、トン
ネル障壁層１３を順次除去して接合部を規定す
る。次に、第１図ｃに示すように、エツチングマ
スク１６を除去した後、プラズマCVD法やスパ
ツタ法により試料全面に二酸化シリコン（SiO2）
を150nｍ被着し、第１の絶縁体層１６を形成す
る。 Next, as shown in FIG. 1b, the mask auxiliary layer 15
After forming an etching mask 16 at a location that will become the upper junction, the mask auxiliary layer 15, second superconductor electrode 14, and tunnel barrier layer 13 are sequentially removed to form the junction, similar to the etching of the multilayer film described above. stipulate. Next, as shown in FIG. 1c, after removing the etching mask 16, silicon dioxide (SiO 2 ) is deposited on the entire surface of the sample by plasma CVD or sputtering.
A thickness of 150 nm is deposited to form the first insulating layer 16.
次にCHF3などを用いた反応性スパツタエツチ
ング法やイオンビームエツチング法での第１の絶
縁体層１７を平坦部の第１の超伝導体電極１２表
面が現われるまでエツチングする。これらの異方
性エツチング法では、エツチングは主に基板面に
対して垂直方向に進行するため、この方向に第１
の絶縁体層１６の初期膜厚の厚い接合部周辺では
エツチング残りを生じ、第１図ｄに示すように接
合部の側壁を第１の絶縁体層１７で被覆した構造
が得られる。その後、５硼酸アンモニウムとエチ
レングリコールの水溶液中で第１の超伝導体電極
１２をアノードとして第１超伝導体電極１２の露
出表面を陽極酸化すると、第１図ｅに示すような
酸化ニオブ（Nb2O5）でなる第２の絶縁体層１８
が形成される。Nb2O5の膜厚は陽極酸化電圧Ｖに
より約2nｍ／Ｖの関係で制御される。 Next, the first insulating layer 17 is etched by a reactive sputter etching method using CHF 3 or the like or an ion beam etching method until the flat surface of the first superconductor electrode 12 is exposed. In these anisotropic etching methods, etching mainly proceeds in the direction perpendicular to the substrate surface, so there is a first step in this direction.
Etching remains around the junction where the initial thickness of the insulator layer 16 is thick, resulting in a structure in which the side wall of the junction is covered with the first insulator layer 17, as shown in FIG. 1d. Thereafter, when the exposed surface of the first superconductor electrode 12 is anodized in an aqueous solution of ammonium pentaborate and ethylene glycol using the first superconductor electrode 12 as an anode, a niobium oxide (Nb 2 O 5 ) second insulator layer 18
is formed. The film thickness of Nb 2 O 5 is controlled by the anodic oxidation voltage V in a relationship of approximately 2 nm/V.
本実施例では、Ｖ＝100（ｖ）で200nｍの
Nb2O5膜を成長させた。NbからNb2O5への体積
膨張は約2.6倍であるから、陽極酸化で消費され
た第１の超伝導体電極１２の膜厚は約80nｍであ
る。 In this example, V = 100 (v) and 200 nm
A Nb 2 O 5 film was grown. Since the volume expansion from Nb to Nb 2 O 5 is approximately 2.6 times, the thickness of the first superconductor electrode 12 consumed by anodic oxidation is approximately 80 nm.
ここでは、陽極酸化のアノードとして第１の超
伝導体電極１２を用いたが、前もつて第１の超伝
導体電極１２の下部に電気的接触を保つて設けた
導体層を用いてもよい。最後に、マスク補助層１
５をリン酸（H3PO4）溶液で選択的に除去した
後、第２の超伝導体電極１４表面をスパツタクリ
ーニングし、第１図ｆに示すように第２の超伝導
体電極１４のパターニングと同様な方法で400n
ｍのNb膜でなる第３の超伝導体電極１９を形成
する。 Here, the first superconductor electrode 12 was used as the anode for anodic oxidation, but a conductor layer previously provided under the first superconductor electrode 12 while maintaining electrical contact may also be used. . Finally, mask auxiliary layer 1
5 is selectively removed with a phosphoric acid (H 3 PO 4 ) solution, the surface of the second superconductor electrode 14 is sputter cleaned, and the second superconductor electrode 14 is removed as shown in FIG. 400n in a similar way to patterning
A third superconductor electrode 19 made of a Nb film of m is formed.
本実施例では、第１図ｄの接合部側壁の被覆保
護の工程で、マスク補助層１５が充分薄いために
この側壁に被着した第１の絶縁体層による突起の
問題はない。また、第１図ｅに示した陽極酸化の
工程で接合部の側壁が第１の絶縁体層１７で被覆
保護されているため、陽極酸化層が接合部まで進
入することがない。そのため、第１の超伝導体電
極１２と第２の超伝導体電極１４との間の電気絶
縁層に第１の超伝導体電極１２の陽極酸化膜を用
いても、接合寸法は異方性ドライエツチング法で
規定されるため高寸法精度で場所的なばらつきの
小さいジヨセフソン素子が形成できる。 In this embodiment, in the step of covering and protecting the side wall of the joint part shown in FIG. 1d, since the mask auxiliary layer 15 is sufficiently thin, there is no problem of protrusions caused by the first insulating layer deposited on this side wall. Further, since the side wall of the joint portion is covered and protected with the first insulating layer 17 in the anodization step shown in FIG. 1e, the anodic oxidation layer does not penetrate into the joint portion. Therefore, even if the anodic oxide film of the first superconductor electrode 12 is used as the electrical insulating layer between the first superconductor electrode 12 and the second superconductor electrode 14, the bonding dimension is anisotropic. Since it is defined by a dry etching method, Josephson elements with high dimensional accuracy and small local variations can be formed.
本実施例では、マスク補助層にSi3N4膜を用い
たが、陽極酸化時にマスク効果のある材料であれ
ば他の絶縁体や半導体膜を用いてもよい。第１、
第２、第３の超伝導体電極として共にNb膜を用
いたが、第１の超伝導体電極には陽極酸化が可能
な窒化ニオブ（NbN）などのNb化合物を、第
２、第３の超伝導体電極には各種の超伝導体材料
を用いることができる。トンネル障壁層にはAl
酸化膜以外に他の金属酸化膜、半導体膜、絶縁体
膜なども適用できる。第１の絶縁体層にはSiO2
膜以外に他の絶縁体膜を用いても何ら問題はな
い。 In this embodiment, a Si 3 N 4 film was used as the mask auxiliary layer, but other insulators or semiconductor films may be used as long as they have a masking effect during anodization. First,
Nb films were used for both the second and third superconductor electrodes, but an Nb compound such as niobium nitride (NbN), which can be anodized, was used for the first superconductor electrode, and an Nb film was used for the second and third superconductor electrodes. Various superconductor materials can be used for the superconductor electrode. Al for tunnel barrier layer
In addition to the oxide film, other metal oxide films, semiconductor films, insulator films, etc. can also be applied. The first insulator layer contains SiO 2
There is no problem even if other insulating films are used in addition to the film.
また、マスク補助層の除去は、この材料および
膜厚の選択により、第２の超伝導体電極のスパツ
タクリーニング時に同じ方法で連続して除去する
ことができる。特に、本実施例で用いたNbのよ
うな酸化性が強く、酸化膜の除去が容易でない材
料を第２の超伝導体電極とする場合に、第２の超
伝導体電極表面に酸化膜を形成しないで被着した
マスク補助層を用いると、第２、第３の超伝導体
電極間の電気接触が容易となる。 Furthermore, by selecting the material and film thickness, the mask auxiliary layer can be removed continuously in the same manner during sputter cleaning of the second superconductor electrode. In particular, when the second superconductor electrode is made of a material such as Nb used in this example, which has strong oxidizing properties and whose oxide film is difficult to remove, an oxide film is formed on the surface of the second superconductor electrode. The unformed deposited mask auxiliary layer facilitates electrical contact between the second and third superconductor electrodes.
（効果）
以上説明したように本発明によれは、第１の超
伝導体電極と第２の超伝導体電極との間の電気絶
縁層に第１の超伝導体電極を陽極酸化膜を用いて
も、接合寸法は異方性ドライエツチング法で規定
されるため高寸法精度で場所的なばらつきの小さ
いジヨセフソン素子が形成できる。しかも、接合
部側壁の被覆の際、第２の超伝導体電極表面は陽
極酸化のマスクとなる範囲で充分薄く、マスク補
助層でマスキングされるため、マスク補助層を除
去した後も接合部周辺に突起がなく平坦な上部配
線が形成できる。(Effects) As explained above, according to the present invention, the first superconductor electrode is formed using an anodic oxide film as the electrical insulating layer between the first superconductor electrode and the second superconductor electrode. However, since the bonding dimensions are determined by an anisotropic dry etching method, a Josephson element with high dimensional accuracy and small local variations can be formed. Moreover, when covering the side walls of the junction, the surface of the second superconductor electrode is sufficiently thin to serve as a mask for anodic oxidation, and is masked by the mask auxiliary layer, so even after the mask auxiliary layer is removed, the area around the junction remains A flat upper wiring can be formed without any protrusions.
第１図ａ〜ｆは本発明のトンネル型ジヨセフソ
ン素子の製造方法を工程順に示す断面図、第２図
ａ〜ｃは従来のトンネル型ジヨセフソン素子の製
造方法を工程に示す断面図である。
図において、１１，２１は基板、１２，２２は
第１の超伝導体電極、１３，２３はトンネル障壁
層、１４，２４は第２の超伝導体電極、１５はマ
スク補助層、１６，２５はエツチングマスク、１
７，２６は第１の絶縁体層または絶縁体層、１
８、は第２の絶縁体層、１９，２７は第３の超伝
導体電極である。
1A to 1F are cross-sectional views showing the manufacturing method of a tunnel-type Josephson device according to the present invention in order of steps, and FIGS. 2A to 2C are cross-sectional views showing the steps of a conventional method of manufacturing a tunnel-type Josephson device. In the figure, 11, 21 are substrates, 12, 22 are first superconductor electrodes, 13, 23 are tunnel barrier layers, 14, 24 are second superconductor electrodes, 15 are mask auxiliary layers, 16, 25 is an etching mask, 1
7 and 26 are first insulator layers or insulator layers, 1
8 is a second insulator layer, and 19 and 27 are third superconductor electrodes.
Claims (1)
層、第２の超伝導体電極、陽極酸化のマスクとな
る範囲で充分薄いマスク補助層を連続形成する工
程、前記マスク補助層上の接合部となる箇所にエ
ツチングマスクを形成し、前記マスク補助層と、
第２の超伝導体電極と前記トンネル障壁層をドラ
イエツチング除去する工程、前記エツチングマス
クを除去した後第１の絶縁体層を被着する工程、
前記第１の絶縁体層をドライエツチングして接合
部の側壁を選択的に前記第１の絶縁体層で被覆す
る工程、前記第１の超伝導体電極の露出表面を陽
極酸化して第２の絶縁体層を形成する工程、前記
マスク補助層を除去した後、前記第２の超伝導体
電極と電気的に接触するように第３の超伝導体電
極を形成する工程を含むことを特徴とするジヨセ
フソン素子の製造方法。1 Step of successively forming a first superconductor electrode, a tunnel barrier layer, a second superconductor electrode, and a sufficiently thin mask auxiliary layer to serve as a mask for anodic oxidation on a substrate, and bonding on the mask auxiliary layer. an etching mask is formed at the location where the mask auxiliary layer and
dry etching away the second superconductor electrode and the tunnel barrier layer; depositing a first insulator layer after removing the etching mask;
dry etching the first insulator layer to selectively cover the sidewalls of the joint with the first insulator layer; and anodizing the exposed surface of the first superconductor electrode to form a second insulator layer. and, after removing the mask auxiliary layer, forming a third superconductor electrode so as to be in electrical contact with the second superconductor electrode. A method for manufacturing a Josephson device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61054950A JPS62213287A (en) | 1986-03-14 | 1986-03-14 | Manufacture of josephson element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61054950A JPS62213287A (en) | 1986-03-14 | 1986-03-14 | Manufacture of josephson element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62213287A JPS62213287A (en) | 1987-09-19 |
| JPH0334237B2 true JPH0334237B2 (en) | 1991-05-21 |
Family
ID=12984941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61054950A Granted JPS62213287A (en) | 1986-03-14 | 1986-03-14 | Manufacture of josephson element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62213287A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60208873A (en) * | 1984-04-03 | 1985-10-21 | Nec Corp | Manufacture of josephson junction element |
-
1986
- 1986-03-14 JP JP61054950A patent/JPS62213287A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60208873A (en) * | 1984-04-03 | 1985-10-21 | Nec Corp | Manufacture of josephson junction element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62213287A (en) | 1987-09-19 |
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