JPH0328074B2 - - Google Patents
Info
- Publication number
- JPH0328074B2 JPH0328074B2 JP61067362A JP6736286A JPH0328074B2 JP H0328074 B2 JPH0328074 B2 JP H0328074B2 JP 61067362 A JP61067362 A JP 61067362A JP 6736286 A JP6736286 A JP 6736286A JP H0328074 B2 JPH0328074 B2 JP H0328074B2
- Authority
- JP
- Japan
- Prior art keywords
- superconductor
- superconductor electrode
- electrode
- resist mask
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002887 superconductor Substances 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 13
- 239000012212 insulator Substances 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000007743 anodising Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 description 9
- 239000010955 niobium Substances 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000010407 anodic oxide Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- OTRAYOBSWCVTIN-UHFFFAOYSA-N OB(O)O.OB(O)O.OB(O)O.OB(O)O.OB(O)O.N.N.N.N.N.N.N.N.N.N.N.N.N.N.N Chemical compound OB(O)O.OB(O)O.OB(O)O.OB(O)O.OB(O)O.N.N.N.N.N.N.N.N.N.N.N.N.N.N.N OTRAYOBSWCVTIN-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- AFYPFACVUDMOHA-UHFFFAOYSA-N chlorotrifluoromethane Chemical compound FC(F)(F)Cl AFYPFACVUDMOHA-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 1
- 235000019404 dichlorodifluoromethane Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 229910000484 niobium oxide Inorganic materials 0.000 description 1
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はトンネル型ジヨセフソン素子の製法に
関し、さらに詳しくは集積回路に適した微小なト
ンネル型ジヨセフソン素子の製法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a tunnel-type Josephson device, and more particularly to a method for manufacturing a minute tunnel-type Josephson device suitable for integrated circuits.
（従来の技術）
代表的な従来例として、エイツチ・クローガー
（H.Kroger）らによつて1981年８月にアプライ
ド・フイジツクス・レターズ（Applied Physics
Letters）の第39巻第３号280〜282頁で発表され
た論文で提案されている方法がある。この方法を
第２図ａ〜ｃの断面図を用いて工程順に説明す
る。第２図ａに示すように、基板２１上にニオブ
Nbでなる第１の超伝導体電極２２、トンネル障
壁層２３、Nbでなる第２の超伝導体電極２４の
３層膜を連続形成する。第１の超伝導体電極２２
および第２の超伝導体電極２４は直流マグネトロ
ンスパツタ法で被着する。トンネル障壁層２３は
シリコン−水素（Si−Ｈ）合金を被着し、熱酸化
して形成する。上記３層膜２２，２３，２４をパ
ターニングして下部配線を形成した後、第２図ｂ
に示すように第２の超伝導体電極２４上の接合部
となる場所にホトレジストでエツチングマスク２
５を形成し、引続き第１および第２の超伝導体電
極２２，２４をアノードとしての第２の超伝導体
電極２４の露出部分をトンネル障壁層まで陽極酸
化し絶縁体層２６を形成する。エツチングマスク
２５を除去した後、第２の超伝導体電極２４の露
出表面をスパツタクリーニングし、第１および第
２の超伝導体電極２２，２４の場合と同様な成膜
法で第３の超伝導体電極２７を被着し、引続き加
工すると第２図ｃに示すようなジヨセフソン素子
が得られる。(Prior art) As a typical conventional example, H. Kroger et al. published Applied Physics Letters in August 1981.
There is a method proposed in a paper published in vol. 39, no. 3, pages 280-282 of Letters). This method will be explained step by step using cross-sectional views of FIGS. 2a to 2c. As shown in FIG. 2a, niobium is deposited on the substrate 21.
A three-layer film consisting of a first superconductor electrode 22 made of Nb, a tunnel barrier layer 23, and a second superconductor electrode 24 made of Nb is successively formed. First superconductor electrode 22
And the second superconductor electrode 24 is deposited by direct current magnetron sputtering. The tunnel barrier layer 23 is formed by depositing a silicon-hydrogen (Si--H) alloy and thermally oxidizing it. After patterning the three-layer films 22, 23, and 24 to form the lower wiring, as shown in FIG.
As shown in FIG.
5 is formed, and then the exposed portion of the second superconductor electrode 24 is anodized to the tunnel barrier layer using the first and second superconductor electrodes 22 and 24 as anodes to form an insulator layer 26. After removing the etching mask 25, the exposed surface of the second superconductor electrode 24 is sputter cleaned, and the third superconductor electrode 24 is deposited using the same film formation method as the first and second superconductor electrodes 22, 24. After application of superconductor electrode 27 and subsequent processing, a Josephson element as shown in FIG. 2c is obtained.
（発明が解決しようとする問題点）
この方法では、第２図ｂに示した陽極酸化の工
程で、酸化は時間とともに等方的に進行するため
エツチングマスク２５下部の第２の超伝導体電極
２４まで一部酸化される。しかもエツチングマス
ク２５下部への酸化層の浸入幅をサブミクロンオ
ーダーで制御するのは容易ではない。従つて、１
〜2μｍ程度の微小接合寸法のジヨセフソン素子
を数多く配した集積回路を作製する場合には、目
標とするジヨセフソン素子の臨界電流値が得られ
ないという問題や、この値のウエーハ内での均一
性が不充分であるという問題を生じる。(Problems to be Solved by the Invention) In this method, in the anodic oxidation step shown in FIG. Partially oxidized up to 24. Moreover, it is not easy to control the width of penetration of the oxide layer into the lower part of the etching mask 25 on the order of submicrons. Therefore, 1
When fabricating an integrated circuit with a large number of Josephson devices with micro junction dimensions of ~2 μm, there are problems such as not being able to obtain the target critical current value of the Josephson devices, and the uniformity of this value within the wafer. This gives rise to the problem of insufficiency.
本発明の目的は、このような従来の欠点を取り
除いたトンネル型ジヨセフソン素子の製法を提供
することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a tunnel-type Josephson device that eliminates such conventional drawbacks.
（問題点を解決するための手段）
本発明によれば、基板上に第１の超伝導体電
極、トンネル障壁層、第２の超伝導体電極を連続
形成する工程、前記第２の超伝導体電極上の接合
部となる箇所にレジストマスクを形成し、前記第
２の超伝導体電極と前記トンネル障壁層をドライ
エツチング除去する工程、熱処理により前記レジ
ストマスクの接触角を減少させる工程、前記レジ
ストマスクを残したまま第１の絶縁体層を被着す
る工程、前記第１の絶縁体層をドライエツチング
して接合部の側壁を選択的に前記第１の絶縁体層
で被覆する工程、前記第１の超伝導体電極の露出
表面を陽極酸化して第２の絶縁体層を形成する工
程、前記レジストマスクを除去した後、前記第２
超伝導体電極と電気的に接触するように第３の超
伝導体電極を形成する工程を含むことを特徴とす
るトンネル型ジヨセフソン素子の製法が得られ
る。(Means for Solving the Problems) According to the present invention, the step of successively forming a first superconductor electrode, a tunnel barrier layer, and a second superconductor electrode on a substrate; a step of forming a resist mask at a location on the body electrode that will become a bonding portion, and removing the second superconductor electrode and the tunnel barrier layer by dry etching; a step of reducing the contact angle of the resist mask by heat treatment; depositing a first insulating layer while leaving the resist mask; dry etching the first insulating layer to selectively cover the sidewalls of the joint with the first insulating layer; a step of anodizing the exposed surface of the first superconductor electrode to form a second insulator layer; after removing the resist mask;
A method for manufacturing a tunnel-type Josephson device is obtained, which includes the step of forming a third superconductor electrode so as to be in electrical contact with the superconductor electrode.
（作用）
本発明では、まず第２の超伝導体電極とトンネ
ル障壁層をドライエツチングして接合部の寸法を
規定し、次に接合部の側壁を第１の絶縁体層で被
覆保護した後、露出した第１の超伝導体電極を陽
極酸化して第１の超伝導体電極と第３の超伝導体
電極との間の電気絶縁のための第２の絶縁体層を
形成する。そのため、陽極酸化の際、従来例のよ
うに酸化が接合部まで及ぶという問題がない。そ
の結果、ドライエツチング技術で規定される高寸
法精度の微小接合を備え、この接合寸法の場所的
なばらつきの小さいジヨセフソン素子の製造が可
能となる。(Function) In the present invention, first, the dimensions of the joint are defined by dry etching the second superconductor electrode and the tunnel barrier layer, and then the side walls of the joint are covered and protected with the first insulating layer. , anodizing the exposed first superconductor electrode to form a second insulator layer for electrical isolation between the first and third superconductor electrodes. Therefore, during anodic oxidation, there is no problem that the oxidation extends to the joints as in the conventional example. As a result, it becomes possible to manufacture a Josephson element that has micro-junctions with high dimensional accuracy defined by dry etching technology and has small local variations in the dimensions of these junctions.
しかも、接合部側壁の被覆保護の際、接触角の
小さいレジストマスク上に第１の絶縁体層を被着
するため、この第１の絶縁体層のエツチング後、
レジストマスク側壁まで被覆されることがない。
そのため、レジストマスクを除去した後も接合部
周辺に突起がなく、平坦な上部配線を形成でき
る。 Moreover, when protecting the sidewall of the joint, the first insulating layer is deposited on the resist mask with a small contact angle, so after etching the first insulating layer,
The side walls of the resist mask are not covered.
Therefore, even after the resist mask is removed, there are no protrusions around the junction, and a flat upper wiring can be formed.
（実施例）
次に本発明を実施例第１図ａ〜ｇの断面図を参
照して説明する。(Example) Next, the present invention will be explained with reference to the cross-sectional views of FIGS. 1a to 1g of Example.
まず、第１図ａに示すように基板１１上に第１
の超伝導体電極１２、トンネル障壁層１３、第２
の超伝導体電極１４から成る３層膜を形成する。
第１および第２の超伝導体電極１２，１４は、共
にスパツタ法や電子ビーム蒸着法により被着した
それぞれ膜厚300nｍ、150nｍのNb膜である。ト
ンネル障壁層１３は、スパツタ法が蒸着法により
被着した膜厚約5nｍのアルミニウムAl膜を純酸
素O2雰囲気中で熱酸化して形成する。 First, as shown in FIG.
superconductor electrode 12, tunnel barrier layer 13, second
A three-layer film consisting of superconductor electrodes 14 is formed.
The first and second superconductor electrodes 12 and 14 are Nb films with a thickness of 300 nm and 150 nm, respectively, deposited by sputtering or electron beam evaporation. The tunnel barrier layer 13 is formed by thermally oxidizing an aluminum Al film with a thickness of about 5 nm deposited by sputtering or vapor deposition in a pure oxygen O 2 atmosphere.
上記３層膜のパターニングは通常のフオトリソ
グラフイ工程を用いて、フロン12（CCl2F2）やフ
ロン13（CF4）をエツチングガスとする反応性ス
パツタエツチング法で行なう。 The three-layer film is patterned by a reactive sputter etching method using Freon 12 (CCl 2 F 2 ) or Freon 13 (CF 4 ) as an etching gas using a conventional photolithography process.
次に、第１図ｂに示すように第２の超伝導体電
極１４上の接合部となる箇所にレジストマスク１
５を形成した後、CCl2F2やCF4による反応性スパ
ツタエツチング法で第２の超伝導体電極１４とト
ンネル障壁層１３を順次除去して接合部を規定す
る。引続き、熱処理によりレジストマスク１５の
接触角を減少させると第１図ｃのようなレジスト
マスク１５形状が得られる。 Next, as shown in FIG.
5, the second superconductor electrode 14 and tunnel barrier layer 13 are sequentially removed by reactive sputter etching using CCl 2 F 2 or CF 4 to define a junction. Subsequently, by reducing the contact angle of the resist mask 15 by heat treatment, a shape of the resist mask 15 as shown in FIG. 1c is obtained.
熱処理温度範囲の下限はレジストパターンの変
形が始まる温度で、上限はレジストパターンのフ
ローが生じる直前の温度である。この温度範囲は
レジストの種類により異なるが、本実施例で用い
たAZ−1350J（米国シツプレーネ社製）では110〜
130℃である。 The lower limit of the heat treatment temperature range is the temperature at which the resist pattern begins to deform, and the upper limit is the temperature immediately before the resist pattern begins to flow. This temperature range varies depending on the type of resist, but in the case of AZ-1350J (manufactured by Situplane, Inc., USA) used in this example, it ranges from 110 to
The temperature is 130℃.
次に、第１図ｄに示すように、レジストマスク
１５を残したままプラズマCVD法やスパツタ法
により試料全面に二酸化硅素（SiO2）を150nｍ
被着し、第１の絶縁体層１６を形成する。次に、
フロン23（CHF3）などを用いた反応性スパツタ
エツチング法やイオンビームエツチング法で第１
の絶縁体層１６を平担部の第１の超伝導体電極１
２表面が現われるまでエツチングする。これらの
異方性エツチング法では、エツチングは主に基板
面に対して垂直方向に進行するため、この方向に
第１の絶縁体層１６の初期膜厚の厚い接合部周辺
ではエツチング残りを生じ、第１図ｅに示すよう
に接合部の側壁を第１の絶縁体層１６で被覆した
構造が得られる。特に本実施例では、レジストマ
スク１５は接触角の小さい形状をもつため、レジ
ストマスク１５側壁まで第１の絶縁体層１６で被
覆されることがない。 Next, as shown in FIG. 1d, 150 nm of silicon dioxide (SiO 2 ) is deposited over the entire surface of the sample by plasma CVD or sputtering while leaving the resist mask 15.
is deposited to form a first insulator layer 16. next,
The first method is the reactive sputter etching method using Freon-23 (CHF 3 ), etc., or the ion beam etching method.
The insulator layer 16 of the flat part of the first superconductor electrode 1
2. Etch until the surface appears. In these anisotropic etching methods, etching mainly proceeds in a direction perpendicular to the substrate surface, so that etching remains in this direction around the junction where the initial film thickness of the first insulating layer 16 is thick; As shown in FIG. 1e, a structure is obtained in which the side walls of the joint are covered with the first insulating layer 16. Particularly in this embodiment, since the resist mask 15 has a shape with a small contact angle, the side walls of the resist mask 15 are not covered with the first insulating layer 16.
その後、五硼酸アンモニウムとエチレングリコ
ールの水溶液中で第１の超伝導体電極１２をアノ
ードとして第１の超伝導体電極１２の露出表面を
陽極酸化すると、第１図ｆに示すような酸化ニオ
ブ（Nb2O5）でなる第２の絶縁体層１７が形成さ
れる。Nb2O5の膜厚は陽極酸化電圧Ｖにより約
2nｍ／Ｖの関係で制御される。 Thereafter, when the exposed surface of the first superconductor electrode 12 is anodized in an aqueous solution of ammonium pentaborate and ethylene glycol using the first superconductor electrode 12 as an anode, niobium oxide ( A second insulator layer 17 made of (Nb 2 O 5 ) is formed. The film thickness of Nb 2 O 5 varies depending on the anodic oxidation voltage V.
It is controlled by a relationship of 2 nm/V.
本実施例では、Ｖ＝100（ｖ）で200nｍの
Nb2O5膜を成長させた。NbからNb2O5への体積
膨張は約2.6倍であるから、陽極酸化で消費され
た第１の超伝導体電極１２の膜厚は約80nｍであ
る。ここでは、陽極酸化のアノードとして第１の
超伝導体電極１２を用いたが、前もつて第１の超
伝導体電極１２の下部に電気的接触を保つて設け
た導体層を用いてもよい。最後に、エツチングマ
スク１５を除去した後、第２の超伝導体電極１４
表面にスパツタクリーニングし、第１図ｇに示す
ように第２の超伝導体電極１４のパターニングと
同様な方法で400nｍのNb膜でなる第３の超伝導
体電極１８を形成する。 In this example, V = 100 (v) and 200 nm
A Nb 2 O 5 film was grown. Since the volume expansion from Nb to Nb 2 O 5 is about 2.6 times, the thickness of the first superconductor electrode 12 consumed by anodic oxidation is about 80 nm. Here, the first superconductor electrode 12 was used as the anode for anodic oxidation, but a conductor layer previously provided under the first superconductor electrode 12 while maintaining electrical contact may also be used. . Finally, after removing the etching mask 15, the second superconductor electrode 14
The surface is spatter cleaned, and a third superconductor electrode 18 made of a 400 nm Nb film is formed in the same manner as the patterning of the second superconductor electrode 14, as shown in FIG. 1g.
本実施例では、第１図ｆに示した陽極酸化の工
程で接合部の側壁が第１の絶縁体層１６で被覆保
護されているため、陽極酸化層が接合部まで進入
することがない。そのため、第１の超伝導体電極
１２と第２の超伝導体電極１４との間で電気絶縁
層に第１の超伝導体電極１２の陽極酸化膜を用い
ても、接合寸法は異方性ドライエツチング法で規
定されるため高寸法精度で場所なばらつきの小さ
いジヨセフソン素子が形成できる。 In this embodiment, since the side wall of the joint is covered and protected by the first insulating layer 16 in the anodization step shown in FIG. 1f, the anodic oxidation layer does not penetrate into the joint. Therefore, even if the anodic oxide film of the first superconductor electrode 12 is used as an electrical insulating layer between the first superconductor electrode 12 and the second superconductor electrode 14, the bonding dimension is anisotropic. Since it is defined by the dry etching method, Josephson elements with high dimensional accuracy and small local variations can be formed.
本実施例では、第１、第２、第３の超伝導体電
極として共にNb膜を用いたが、第１の超伝導体
電極には陽極酸化が可能な窒化ニオブ（NbN）
などのNb化合物を、第２、第３の超伝導体電極
には各種の超伝導体材料を用いることができる。
トンネル障壁層にはAl酸化膜以外に他の金属酸
化膜、半導体膜、絶縁体膜なども適用できる。ま
た、第１の絶縁体層にはSiO2膜以外に他の絶縁
体層を用いても何ら問題はない。 In this example, Nb films were used as the first, second, and third superconductor electrodes, but the first superconductor electrode was made of niobium nitride (NbN), which can be anodized.
Various superconductor materials can be used for the second and third superconductor electrodes.
In addition to the Al oxide film, other metal oxide films, semiconductor films, insulator films, etc. can also be used as the tunnel barrier layer. Further, there is no problem in using an insulating layer other than the SiO 2 film for the first insulating layer.
（効果）
以上説明したように本発明によれば、第１の超
伝導体電極と第２の超伝導体電極との間の電気絶
縁層に第１の超伝導体電極の陽極酸化膜を用いて
も、接合寸法は異方性ドライエツチング法で規定
されるため高寸法精度で場所的なばらつきの小さ
いジヨセフソン素子が形成できる。しかも、接合
部側壁の被覆の際、接触角の小さいレジストマス
クを用いることで、レジストマスクを除去した後
も接合部周辺に突起がなく平担な上部配線が形成
できる。(Effects) As explained above, according to the present invention, the anodic oxide film of the first superconductor electrode is used as the electrical insulating layer between the first superconductor electrode and the second superconductor electrode. However, since the bonding dimensions are determined by an anisotropic dry etching method, a Josephson element with high dimensional accuracy and small local variations can be formed. Furthermore, by using a resist mask with a small contact angle when covering the side wall of the joint, a flat upper wiring can be formed without protrusions around the joint even after the resist mask is removed.
第１図ａ〜ｇは本発明のトンネル型ジヨセフソ
ン素子の製法を工程順に示す断面図、第２図ａ〜
ｃは従来のトンネル型ジヨセフソン素子の製造方
法を工程に示す断面図である。
図において、１１，２１は基板、１２，２２の
第１の超伝導体電極、１３，２３はトンネル障壁
層、１４，２４の第２の超伝導体電極、１５，２
５はレジストマスク、１６，２６は第１の絶縁体
層または絶縁体層、１７は第２の絶縁体層、１
８，２７は第３の超伝導体電極である。
FIGS. 1a to 1g are cross-sectional views showing the manufacturing method of the tunnel-type Josephson device of the present invention in order of steps, and FIGS.
FIG. 1c is a cross-sectional view showing the steps of a conventional method for manufacturing a tunnel-type Josephson device. In the figure, 11, 21 are substrates, 12, 22 are first superconductor electrodes, 13, 23 are tunnel barrier layers, 14, 24 are second superconductor electrodes, 15, 2
5 is a resist mask, 16 and 26 are first insulator layers or insulator layers, 17 is a second insulator layer, 1
8 and 27 are third superconductor electrodes.
Claims (1)
層、第２の超伝導体電極を連続形成する工程、前
記第２の超伝導体電極上の接合部となる箇所にレ
ジストマスクを形成し、前記第２の超伝導体電極
と前記トンネル障壁層をドライエツチング除去す
る工程、熱処理により前記レジストマスクの接触
角を減少させる工程、前記レジストマスクを残し
たまま第１の絶縁体層を被着する工程、前記第１
の絶縁体層をドライエツチングして接合部の側壁
を選択的に前記第１の絶縁体層で被覆する工程、
前記第１の超伝導体電極の露出表面を陽極酸化し
て第２の絶縁体層を形成する工程、前記レジスト
マスクを除去した後、前記第２の超伝導体電極と
電気的に接触するように第３の超伝導体電極を形
成する工程を含むことを特徴とするトンネル型ジ
ヨセフソン素子の製法。1 Step of sequentially forming a first superconductor electrode, a tunnel barrier layer, and a second superconductor electrode on a substrate, forming a resist mask at a location on the second superconductor electrode that will become a joint. , removing the second superconductor electrode and the tunnel barrier layer by dry etching, reducing the contact angle of the resist mask by heat treatment, and depositing a first insulating layer while leaving the resist mask. the first step of
selectively covering the sidewalls of the joint with the first insulating layer by dry etching the insulating layer;
anodizing the exposed surface of the first superconductor electrode to form a second insulator layer, after removing the resist mask, making electrical contact with the second superconductor electrode; 1. A method for manufacturing a tunnel-type Josephson device, comprising the step of forming a third superconductor electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61067362A JPS62224989A (en) | 1986-03-27 | 1986-03-27 | Manufacture of tunnel type josephson device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61067362A JPS62224989A (en) | 1986-03-27 | 1986-03-27 | Manufacture of tunnel type josephson device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62224989A JPS62224989A (en) | 1987-10-02 |
| JPH0328074B2 true JPH0328074B2 (en) | 1991-04-17 |
Family
ID=13342827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61067362A Granted JPS62224989A (en) | 1986-03-27 | 1986-03-27 | Manufacture of tunnel type josephson device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62224989A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60208873A (en) * | 1984-04-03 | 1985-10-21 | Nec Corp | Manufacture of josephson junction element |
-
1986
- 1986-03-27 JP JP61067362A patent/JPS62224989A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62224989A (en) | 1987-10-02 |
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| EXPY | Cancellation because of completion of term |