JPS60208837A - Taper etching method of thin film - Google Patents

Abstract

PURPOSE:To prevent the yield of an inverted part on a semiconductor layer beneath a mask pattern, by forming a thin film on the mask pattern, whose cross- sectional shape is vertical, thereafter performing anisotropic etching. CONSTITUTION:The pattern of an ion-implanting mask layer 3 is formed on a semiconductor layer 2. At this time, the cross-sectional shape of the mask is vertical. Then, a polysilicon film 5 is isotropically formed thereon. Thereafter, the entire surface of the polysilicon layer 5 is etched by anisotropic etching. Thus, a shape, where the polysilicon layer 5 remains at the step of the mask 3, is obtained. The anisotropic etching is further continued. Then, the semiconductor layer 2 reflects the shape of the polysilicon layer 5, which remains at the stepped part of the mask layer 3, and the layer 2 is etched in a tapered shape.

Description

Detailed Description of the Invention (Field of Mining Application) The present invention relates to a thin film taper etching method. (Prior art and its problems) In general, thin film M and IS transistors are monocrystalline semiconductors formed on an insulating substrate. It is made using a thin film,
SO8 (5ilicon on 5apphire or 5ilicon on 5pinel), SOI
(5 silicon on Ilusulator) and the like are typical thin film transistors, but the SO8 type will be explained below as an example.

Conventionally, in the manufacturing method of thin-film MIS transistors (typified by the SO8 type), one of the element isolation methods is to remove unnecessary parts of the semiconductor layer, such as Jllll or crystalline silicon film, formed on an insulating substrate such as sapphire. There is a method of removing it entirely and forming an island of semiconductor layer.

FIG. 1 is a schematic diagram of the manufacturing process. Here, 1 is an insulating substrate, 2 is a semiconductor layer, 3 is an ion implantation mask layer, and 4
denote impurity diffusion layers; in particular, in the case of SO8 type, 1 corresponds to a sapphire substrate, 2 corresponds to a silicon layer, and 3 corresponds to a silicon oxide film.

(a) is a cross-sectional view of a state f1 in which an ion implantation mask layer 3 is patterned on the semiconductor layer 2 by seven photoresist etching steps and an etching rate.

(bl is a cross-sectional view of the semiconductor layer 21t etched through the ion implantation mask layer 3. (c) is a cross-sectional view of the semiconductor layer 21t etched by ion-implanting impurities with the ion implantation mask layer remaining. It is a cross-sectional view of a state in which a diffusion layer 4 is formed on the side surface.Here, the diffusion layer 4 on the side surface is formed to suppress leakage current on the side surface.For example, in the case of an N-channel MIS transistor, a In the case of a transistor, a V group element such as P is implanted.

A major feature of the conventional process for forming such semiconductor islands is the taper etching of the semiconductor layer. This is because if the taper is formed, disconnection of the wiring can be prevented. In the case of the SO8 type, taper etching of the silicon layer was performed using a strong alkaline solution such as hydrazine or KOH.

For example, in the case of hydrazine, the plane orientation of the silicon surface is (10
0), the etching rate is slow as a cross section (111
) Can be exposed and taper etched. However, it is difficult to accurately confirm the end point of this etching, and there is also unevenness in the silicon film thickness within the wafer surface, so over-etching is inevitable. SO8 and S
The OI single crystal silicon film does not have good crystallinity as the single crystal silicon substrate, and this is probably due to stress being applied to the film. It has a tapered shape.

This figure is a schematic cross-sectional view of SO8 etched with about 70"C of heptadazine. In the figure, 1.2 is the same as in Fig. 1, and the solid line 5 is about 1 from just etching.
Over 0%, broken #j! 6 corresponds to the silicon cross section when etched by about 80% over, and one point g line 7 corresponds to the silicon cross section when etched by 160% over. As you can see, when over-etching is 160%, the side faces are in the shadow of the mask and it is impossible to implant ions on the sides, and when over-etching is 80%, it is only about 50%, 10 Even when it is over %, it is still incomplete. In general, in order to perform sufficient ion implantation on the side surfaces, an error of about ±lθ% is not allowed for a certain optimum etching time, and furthermore, it is impossible to monitor the etching state with that precision with conventional methods. This was the cause of not being able to prevent side current leaks with good reproducibility. Moreover, when etching a single crystal thin wX taber which is not good in terms of electric field concentration, wire breakage in aluminum wiring, or deterioration of patterning accuracy, the conventional method causes unfavorable situations such as those mentioned above.

(Objective of the invention) The object of the present invention is to eliminate the above-mentioned drawbacks and to simplify the process.
- It is an object of the present invention to provide a thin film taper etching method that can also be used for thin films with good crystallinity, polycrystalline films, and amorphous thin films.

(Structure of the Invention) According to the present invention, in a method of taper etching a thin film formed on a substrate, etching in the direction perpendicular to the surface of the substrate can act as a mask against anisotropic etching in which etching in the direction horizontal to the surface of the substrate is faster. A mask pattern having a vertical cross-sectional shape is formed on the thin film, and then a thin film is formed isotropically on the anisotropic etching, and the etching distance is approximately equal to that of the semicircular film. A method for taper etching a thin film is obtained, characterized in that the thin film is tapered etched by performing anisotropic etching.

(Example) Hereinafter, the present invention will be described in detail according to an example in which the present invention is applied to an element isolation step in a method for forming an SO8 type transistor.

FIGS. 3(a) to (dl) are schematic cross-sectional views shown to explain the basic method of the present invention. Here, l is a sapphire substrate, 2 is a single crystal silicon layer, and 3 is a silicon oxide layer. The film 5 corresponds to a polysilicon film.

First, a pattern of silicon oxide film 3 is formed on single crystal silicon layer 2. (FIG. 3(a)) Furthermore, the silicon layer 2
The film thicknesses of the silicon oxide film 3 and the silicon oxide film 3 were approximately equal. The thickness of the silicon layer 2 is 0.4 μm1 The thickness of the silicon oxide film 3 is 0.
．． It is 5 μm. At this time, since the cross-sectional shape of the silicon oxide film 3 needs to be vertical, a resist is used as a mask to form an anisotropic dry etching pattern. The etching conditions are shown in the table below.

Next, a polysilicon film 5 is formed thereon (FIG. 3(b)
)) Here, the thickness of the polysilicon film 5 is 0.5 μm. It is advantageous to use an isodirectional forming method such as the CVD method as the method for forming the polysilicon film 5, and as shown in FIG.
It becomes possible to increase the thickness of the polysilicon film when viewed from the vertical direction. In this case, immediately after the surface of the silicon layer 2 is etched with hydrofluoric acid to prevent the formation of a yellow layer such as a silicon oxide film between the polysilicon film 5 and the underlying silicon layer 2, the polysilicon film 5 is removed. It is better to form 5 pieces.

Next, the entire surface of the polysilicon film 5 is etched by anisotropic dry etching. The etching conditions are shown in the table below.

Then, as shown in FIG. 3(c), a shape is obtained in which the polysilicon film 5 remains at the step of the underlying silicon oxide film 3.

Further, etching was performed under the same conditions using the anisotropic dry etching process until the underlying silicon layer 1 was etched (Fig. 3(d)). Etching speed of silicon and silicon oxide film is 800^/min each.
, 1'l 00^/min, 130''A/mi
Since the underlying silicon layer 2 is etched with a taper, the shape approximately reflects the shape of the remaining polysilicon film 5 in FIG. 3(e). The cross-sectional shape after etching has no reverse taper, and there is almost no over-etching on the sides. The silicon oxide film 3 may also be etched to some extent, but the thickness of the film is sufficient to be used as a mask.

Therefore, with the present invention, it is possible to obtain a shape that allows ion implantation to be reliably implanted into the side surfaces without the problem of over-etching on the side surfaces that occurs when using hydrazine oxide, and to prevent later wiring disconnection and box boundaries. Kanaka is avoided.

As described above, the present invention solves problems such as leakage current and wiring disconnection, and uses a practical method that enables high integration.

The above description has been made using an SO8 type thin film 1V11s) transistor as an example;
) It is obvious that it can be used for taper etching of transistors or generally single crystal films with slightly low crystallinity formed on substrates. 1 and quality membranes can also be used.

The anisotropic etching used in the examples is anisotropic dry etching, which has the condition that etching in the direction perpendicular to the substrate surface is faster than etching in the direction horizontal to the substrate surface. This may be done using another etching method.

- Similarly, the polysilicon film 5 formed by the CVD method is thick (formed) when viewed from the vertical direction at the stepped portion, and is a thin film whose etching rate is almost equal to that of the underlying semiconductor film in the anisotropic etching. If conditions are met, it may be formed by another method such as sputtering, or a different thin film may be used.

Further, according to the present invention, there is an advantage in selecting the conditions for anisotropic etching, the grain quality and thickness of the layer to be etched, etc.
It is also possible to obtain an arbitrary taper angle of the etched cross section of the semiconductor layer.

[Brief explanation of the drawing]

Figures 1 (a), (bl, and c) are schematic cross-sectional views of conventional manufacturing processes. Figure 2 is a schematic cross-sectional view when a silicon layer is over-etched with hydrazine using a silicon oxide film as a mask. Figure 3 (al, (bl, (
e) and (d) are schematic cross-sectional views shown to explain the basic method of the present invention. In the figure, 1 is an insulating substrate, 2 is a semi-coated layer, and 3 is an ion implantation mask layer. In particular, these correspond to a sapphire substrate, a silicon layer, and a silicon oxide film, respectively, in the case of SO8 type. In addition, 4 is an impurity diffusion layer, 5 (1 polysilicon film is removed. 1.--1 Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] In the method of taper etching a thin gold film formed on a substrate, a mask pattern having a vertical cross-sectional shape is used as a mask for anisotropic etching in which the etching in the direction perpendicular to the substrate surface is faster than the etching in the horizontal direction of the substrate surface. by forming on a thin film, then uniformly forming thereon a thin layer having an etching rate approximately equal to that of the semiconductor film for the anisotropic etching, and then performing the cotropic etching. A method for taper etching a thin film, characterized in that the thin film is tapered etched.