JPS60206269A - Separating circuit for vertical synchronizing signal - Google Patents

Abstract

PURPOSE:To eliminate the need for an external capacitor such as a low-pass filter and a DC coupling and to decrease the number of pins at the time of IC- implementation by generating a pulse whose pulse width is between the pulse width within a vertical synchronism period and the pulse width of a pulse outside of a vertical synchronizing signal synchronously with pulse edges of a composite synchronizing signal, and frequency-separating the vertical synchronizing signal from the composite synchronizing signal. CONSTITUTION:When a negative composite synchronizing signal is inputted to an input terminal 12, a one-shot multivibrator 10 is triggered with the negative edge of the composite synchronizing signal to generate an output Q. The width (t) of this pulse is set to a value between the pulse width to of a pulse within the vertical synchronism period T and pulse width t1 and t2 of a pulse which is not within the vertical synchronism period. The vertical synchronizing signal appears at the output Q of a D latch 11 because the composite synchronizing signal supplied to a data input D is latched successively with output pulses of the one-shot multivibrator 10.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical synchronization signal separation circuit, and particularly to a frequency separation circuit that separates a vertical synchronization signal from a composite synchronization signal.

1" Good 1 Conventionally, as a circuit of this type, there is a circuit shown in FIG. is a DC coupling], 5 and 6 are bias resistors, 7 is a waveform shaping transistor, 8
is an output resistance, and 9 is a vertical synchronization signal output terminal.

In such a vertical synchronization signal separation circuit, when a composite synchronization signal of negative polarity as shown in FIG. A signal with a waveform as shown in FIG. 2 (b+) is obtained by the low-pass filter 2.3. On the other hand, the base of the transistor 7 is provided with an appropriate bias to be cut off when there is no signal by the resistor 5.6. When a signal with a waveform as shown in FIG. 2 is applied to the base of J3 through the coupling capacitor 4, the transistor 7 is turned on during the negative pulse period.
A vertical synchronizing signal as shown in FIG. 2(C) is obtained at the output terminal 9 by the resistor 8.

Such a frequency separation circuit includes a low-pass filter capacitor 3 and a coupling capacitor 4, so if the circuit is integrated into an IC, these capacitors must be externally attached.

Therefore, when converting to IC, the number of IC bins increases,
It also has the disadvantage of being disadvantageous in terms of mounting space.

11 Column "W" This invention was made to eliminate the above-mentioned drawbacks of the conventional method. Taking advantage of the large size, we can digitally separate the vertical synchronization signal and get 1! The purpose of this invention is to provide a vertical synchronization signal separation circuit.

According to the vertical synchronization signal separation circuit according to the present invention, a pulse whose pulse width is between the magnitude of the pulse width of a pulse within the vertical synchronization period and the magnitude of the pulse width of a pulse outside the vertical synchronization signal is The apparatus includes a pulse generating means that generates a pulse in synchronization with a pulse edge of the composite synchronous signal, and a separation circuit that uses the pulse generated by the pulse generating means to divide the vertical synchronous signal from the composite synchronous transmission by a frequency. ing.

Example FIG. 3 is a circuit diagram of an embodiment of the present invention.

This vertical synchronization signal separation circuit consists of a one-shot multivibrator 10 and a D latch 11, and an input terminal 12 to which a composite synchronization signal is supplied is connected to a negative edge trigger input T of the one-shot multivibrator 1o. , is connected to the data input of D-lap 11. The output Q of the one-shot multivibrator 10 is connected to the negative edge trigger input T of the D latch 11, and the output Q of the D latch 11 is connected to the output terminal 13.
It is connected to the.

In this vertical synchronization signal separation circuit J, when a composite synchronization signal of negative polarity as shown in Fig. 4 (ω) (Fig. 2 (composite synchronization 4i of ω; same as SE) is input to the input terminal 12, , the one-shot multivibrator 10 is triggered by the negative edge of the composite synchronization signal, and a pulse as shown in FIG. The value is set to be between the pulse width to of the pulse and the pulse width t1 and [2 of the pulse outside the vertical synchronization period.

That is, the pulse width t is set to be between the pulse width to and tl, and between the pulse width to and the pulse width (2).

The output of the one-shot multivibrator 10 is supplied to the negative edge trigger input T of the D latch 11,
-715', a composite synchronization signal is input to the data input of the D latch 11. In the D-latch 11, the composite synchronization signal supplied to the data input terminal is sequentially latched by the output pulse of the one-shot multivibrator 10, and as a result, the output Q of the D-latch 11 is as shown in FIG. 4(C).
A vertical synchronizing signal as shown in J is obtained.

FIG. 5 is a circuit diagram of another embodiment of the present invention.

This vertical synchronization signal separation circuit consists of a one-shot multivibrator 14, a delay circuit 15 (for example, a one-shot multivibrator), an OR gate 1-16, a one-shot multivibrator 17, etc. The supplied input terminal 18 is connected to the negative edge trigger T of the one-shot multi-by-break 14 and the input terminal of the delay circuit 15. The output Q of the one-shot multivibrator 14 and the outputs of the delay circuit 11 are respectively connected to the input terminals of the OR gate 16, and the output of the OR gate 1G is connected to the negative edge trigger T of the one-shot digital vibrator 17. , one-shot multivibrator 1
The output 0 of 7 is connected to the output terminal 19.

In such a vertical synchronization signal separation circuit, input terminal 1
8, a composite synchronization signal of negative polarity as shown in FIG. 6 (ω) [FIG. 2 (a) and FIG.
When the same] is input to the synchronization signal, the one-shot multivibrator 14 is triggered by the negative edge of the synchronization signal to the composite 1, and a pulse as shown in the sixth output is generated at the output Q, and the OR gate 16 is input. As in the embodiment shown in FIG. 3, the width t of this pulse is set to a value J, which is the difference between the pulse width of a pulse within the vertical synchronization period T and the pulse width of a pulse outside the vertical synchronization period. On the other hand, the composite synchronization signal is delayed in a delay circuit 15, and this delayed output is inputted to an OR gate 16 and OR
A pulse as shown in FIG. 6(C) is obtained at the output of the gate 1G. By supplying this pulse to the negative trigger input T of the one-shot multivibrator 17, a vertical synchronizing signal as shown in FIG. 6 is obtained at the output terminal Q. According to this embodiment, since the delay circuit 15 and the OR gate 16 are used, time races at negative edges can be avoided.

FIG. 7 is a circuit diagram of still another embodiment of the present invention.

This vertical synchronization signal separation circuit consists of a one-shot multivibrator 20 and a D latch 21, and an input terminal 22 to which a composite synchronization signal is supplied is connected to the positive edge 1-rigger input T of the one-shot multivibrator 20, It is connected to the D-lap 21 data port. The output Q of the one-shot multivibrator 2o is connected to the positive edge trigger input T of the D wrap 21.
The output Q of the latch 21 is connected to the output terminal 23.

In such a vertical-to-vertical JIIJ signal separation circuit, when a composite sync signal of negative polarity (J shown in Fig. 2) is input to the input terminal 22, The one-shot multivibrator 2o is triggered by the phase-indeterminate positive edge of the digital synchronization signal, and a pulse similar to that shown in FIG. 8 is generated at the output d. The width t of this pulse is equal to the pulse width of the pulse within the vertical synchronization period T, as in the embodiments of FIGS. 3 and 5! Ti - Set the pulse width of the pulse outside the direct synchronization period to be between 11 and 11.

The protrusion of the One Shot Multivibrator 2o is]
) is applied to the positive edge trigger input T of latch 21, while a composite synchronization signal is applied to the data input of D latch 21. In the D-latch 21, the composite synchronization signal supplied to the data input is sequentially latched at the positive edge of the output pulse of the one-shot multivibrator 20, and as a result, the output Q of the D-wrap 21 is as shown in FIG. 8(C). A vertical synchronization signal as shown in is obtained.

In all the embodiments described above, a case has been described in which a composite synchronization signal of negative polarity is handled, but it is also possible to divide the vertical synchronization signal by similar operations for a composite synchronization signal of positive polarity.

As mentioned above, if this invention is used, there is no need for external capacitors such as low-pass filters and DC coupling, so it is possible to save the number of bins when implementing ICs, and it is possible to reduce the number of bins when implementing. He has the right advantage in terms of space.

It also has the advantage that it is not necessary to add an analog operation circuit to the digital circuit, such as when a graphics microcomputer or the like handles external synchronization signals.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional vertical synchronization signal separation circuit, FIG. 2 is a waveform diagram for explaining the operation of the circuit in FIG. 1, and FIG.
The figure shows one embodiment of the present invention, FIG. 4 is a waveform diagram for explaining the operation of the embodiment of FIG. 3, and FIG. 5 is a diagram showing another embodiment of the present invention. , FIG. 6 is a waveform diagram for explaining the operation of the embodiment of FIG. 5, FIG. 7 is a diagram showing still another embodiment of the present invention, and FIG. 8 is a waveform diagram for explaining the operation of the embodiment of FIG. 7. FIG. Explanation of symbols for type 12 parts 10.14, 17.20...One-shot multivibrator 11.21...D latch 12.18.22...Input terminal 13.19.2
3...Output terminal 15...Delay circuit 16...OR gate Applicant Pioneer Corporation Agent Patent attorney Motohiko Fujimura So>1UjJ Curtain 2 (c)

Claims (3)

[Claims] (1) A vertical synchronization signal separation circuit that separates a vertical synchronization signal from a composite synchronization signal in which the pulse width of the pulse within the vertical synchronization period is larger than the pulse width of the pulse outside the vertical synchronization period, A pulse whose magnitude is between the pulse width of a pulse within the vertical synchronization period and the pulse width of a pulse outside the vertical synchronization period is generated in synchronization with the pulse edge of the composite synchronization signal. 1. A vertical synchronizing signal separation circuit comprising: a pulse generating means for generating a vertical synchronizing signal; and a separating means for frequency-separating a vertical vertical synchronizing signal from the composite synchronizing signal using the pulse generated by the pulse generating means. (2) The pulse generating means is a one-shot multivibrator, and the separating means uses a pulse edge of a pulse generated by the pulse generating means as a trigger input,
2. The vertical synchronization signal separation circuit according to claim 1, wherein the composite synchronization signal is used as a data input. (3) The pulse generation means is a one-shot multivibrator, and the separation circuit includes a delay circuit for delaying the composite synchronization signal, and a composite synchronization signal delayed by the delay circuit and generated by the pulse generation means. An OR gate that takes OR with the pulse and this O
1. A vertical synchronizing signal separation circuit according to item 1 of the special request, characterized in that it consists of a one-shot multivibrator that receives the output pulse of the R gate as input.