JPS60205897A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To produce an initial defect in a short period and to shorten the screening time by controlling an activation signal distributing circuit which supplies the activation signal to one of memory array blocks and then supplying the activation signals simultaneously to >=2 blocks. CONSTITUTION:A distributing circuit 5 impresses the input activation signals phi0 to the row decoder and controller parts 21 and 31 or 22 and 32 in response to addresses A0 and A0' given from an address buffer 4 and set at ''1'' and ''0'' or vice versa. Then a memory array 11 or 12 which is divided into blocks is used selectively. When an external signal psiT is impressed to the buffer 4, both addresses A0 and A0' are set at 0. At the same time, the signals phi0 are supplied simultaneously to circuits 21 and 31 as well as 22 and 32 respectively. Then both arrays 11 and 12 are selected to produce an initial defect in a short period for a performance test at a plant. This can shorten the screening time of non-defective/defective.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device in which a memory array is divided into a plurality of blocks to reduce power consumption.

[Technical background of the invention and its problems] The development of semiconductor integrated circuits (ICs) has been remarkable in recent years, and particularly the progress in the field of memory has been remarkable. The field of dynamic RAM is where integration is progressing the most, and 256-bit MOS dynamic RAM is currently being commercialized.

There is no doubt that the memory size will further increase to 1M bits and 4M bits.

At the factory, ICs are tested for a certain period of time, and only good products are provided to users, excluding those that are defective. This is because the failure rate of a product generally shows a change over time as shown in FIG. That is, most failures occur during the early stages of operation, and after long-term use, the failure rate increases due to fatigue of various parts. Therefore, by using the initial failure period as an operation test period and excluding those that quickly become defective during operation before shipping only non-defective products, it is possible to provide users with products that have an extremely low failure rate. For conventional products, such as 64kbit dynamic RAM, the time required to test the period during which initial failure occurs is several tens of hours.
0 hours is sufficient, and it is possible to check for initial defects by testing for 2 to 3 days. This operation test is conducted at a voltage and temperature higher than the power supply voltage actually used so that defects are likely to occur, but it still requires several tens of hours. 64 with dynamic RAM,
All memory cells can be refreshed in 128 refresh cycles, but 256 refresh cycles are the mainstream in dynamic RAM, which is twice as many cycles. In this case, the probability that the memory cell will be accessed is also 1/2 and 5
Therefore, the time during which voltage is applied to the memory cell during operation is 1
Since it is 1/2 of 28 refresh cycles,
The initial failure occurrence period is 64 times longer than that of dynamic RAM. Conventionally, the initial failure occurrence period was within several tens of hours, but now it is over 100 hours. 1M
If the double refresh cycle (512 refresh cycles) becomes mainstream for bit dynamic RAM, the initial failure period will double, requiring several days to weeks just for operational testing, and the cost required for testing will increase. However, problems such as a delay in responding to the market arise due to an increase in the inventory period.

Therefore, during operation tests, it is necessary to devise ways to pass the initial failure occurrence period in as short a time as possible.

[Object of the Invention] The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a semiconductor and a memory device having a circuit system that can generate initial defects in a short period of time and select defective products during an operation test. With the goal.

[Summary of the Invention] For the purpose of reducing current consumption when increasing the scale, the present invention divides a memory array into a plurality of blocks as a basic configuration of a semiconductor memory device, and blocks any one block by inputting an external address. A method is adopted in which blocks are selected for write and read operations. The present invention provides such a storage device with means for simultaneously activating and operating two or more of a plurality of blocks during an operation test before shipment, thereby making it possible to screen out initial failures in a short period of time. This is a characteristic feature.

[Effects of the Invention] According to the present invention, the operation test period required for initial failure occurrence,
In other words, it is possible to shorten the period of screening for defective products, thereby reducing the cost required for testing and the time required from production to shipment, allowing for immediate response to user needs. Benefits can be obtained. It is also possible to shorten the time required for functional checks.

[Embodiments of the invention] The present invention will be described in detail below using the drawings.

FIG. 2 shows the main structure of a MOS dynamic RAM according to an embodiment. In this embodiment, the memory array is divided into two blocks 11, 12 and integrated. Each memory array block 11, 12 includes a well-known memory cell array and a group of sense amplifiers, and for controlling each, row decoders 21, 22 and a control circuit 3s.
, 32 are provided. 4 is an address buffer, which generates an internal address signal for memory array selection in response to an external address input. 5 is an activation signal φ for selectively driving the memory array blocks 11 and 12.
0 as the internal address signal Ao.

This is a distribution circuit for distribution according to Ao. During normal operation, one of Aa and An is '1'' and the other is 'ON'.
Therefore, the activation signal φ0 is applied to the row decoder 2.
1. Control circuit 31 side or row decoder 22,
The signal is supplied only to either side of the control circuit 3.2.

In addition to the address input, an external control signal vT is input to the address buffer 4 from six external signal input bins. When this control signal v is input, the outputs An and An of the address buffer 4 are controlled to become "0" at the same time, and as a result, the activation signal distribution circuit 5 transmits the activation signal φ0 to the memory array block 11. .12 control circuit sections.

Specific circuit examples of each part will be explained using FIGS. 3 to 5. FIG. 3 shows an example of a dynamic address buffer 4 configured using an enhancement-type MO8Tr.
o, outputs the output of Ao. The timing of this operation is as shown in FIG. φp is a precharge clock. Here, shorting MOS transistors Ql and Q2 are provided at the output stage of this address buffer and at the preceding stage.

It is different from normal in that Q3 and Q4 are provided. A signal φp having an opposite phase to the precharge signal φp is selectively supplied to the gates of these transistors 01 to Q4 via MOS transistors Q5 and Qs. This MOS transistor Qs.

The aforementioned external control signal vT controls the gate of Qs.
It is. That is, if 14/ is at a high level, the output Ao
, An are both O"', and when ψT is low level, Ao, /'l becomes 1111I, " according to the address input.
0”.

In FIG. 6, the signal state during the test operation is indicated by a broken line.

FIG. 4 shows a specific example of the distribution circuit 5. 07 to Q14 are all E type MOS transistors, and during normal operation when one of the internal address signals AO and An becomes "1" and the other becomes 1101+ after the precharge clock φp becomes high level, the MOS transistor Q7 , Qe is on, so the MOS transistor Qs s
, Qt4 is turned on, and the activation signal φ0 is selectively supplied to either the memory array block 11 side or the memory array block 12 side. On the other hand, during the test operation when vT is applied and An = Ao = "O", MOS transistors Qs:l and Q14 are turned on at the same time, and the activation signal φ0 is supplied to both sides of the memory arrays 11 and 12 at the same time. become.

FIG. 5 shows a specific example of a row decoder. During normal operation, the output of the part where all internal address inputs in the row decoders 21 and 22 are 0'' becomes high level, and one word line WL is selected. During an operation test, An = An
= "O", there is an address where the output of both row decoders 21 and 22 becomes high level at the same time, and word lines WL are selected one by one in both memory arrays 11 and 12 at the same time. .

Next is a method of applying the external control signal vT, which is applied from outside the chip using an NC bin (No Connection P In, ie, a bin that is not connected to any internal circuit according to the specifications). As specific examples, three methods shown in FIG. 7 can be considered. (a) is a method in which ψ■ is applied from the NC bin 6 through a fuse 7 such as poly S1. After the overload test, the fuse 7 is fused with a laser, the NC bottle and the internal circuit are disconnected, and the product is shipped. In this method, a laser wavelength that is transparent to the packaging material must be selected to blow the fuse after an overload test of the packaged IC. Alternatively, it is necessary to use a package material that is transparent to the laser beam or to open a window.

Method (b) is a method that does not use laser light,
Applying vT from the NC bottle 6 through the fuse 7 is the same as in (a), but after the overload test, a high voltage is applied to the NC bottle and the fuse 7 is blown. The fusing current is passed through the resistor 8. With this method, it is also possible to conduct a trial analysis after packaging. In the method (C), a vT multiplied signal is applied from the NC bin 6 to the memory cell selection address buffer via the switching transistor 9 having a floating gate structure. In advance, at the packaging stage, apply a high negative voltage to the control gate from the terminal 10 to inject holes into the floating gate of the transistor 9, lower the threshold value, and turn on the transistor 9. Allow the signal from NC Bin 6 to be applied to the address buffer. An overload test is performed in this state, and by irradiating X-rays from outside the package, the holes in the floating gate of transistor 9 are recombined with electrons, the threshold is increased, and transistor 9 is
The product is shipped in the FF state.

In FIG. 7, all the signals of V are applied from the NC bin, but this can also be realized by sharing the address bin, data input, data output bin, or chip enable bin.

As described above, according to the above embodiment, initial failure screening of a large-scale dynamic RAM can be performed in a short time.

In the above explanation, we took an example in which the memory array was divided into two blocks, but if the memory array is divided into three or more blocks, some or all of these blocks may be operated simultaneously during testing. The present invention is also effective in this case. It's a good idea to turn the external signal into
For example, applying a high voltage to the memory plate to test the oxide film withstand voltage can be applied to the C bin or other address input bins, data input bins, data output bins, and write enable bins only during testing. It is also effective when doing.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the change in failure rate of general products over time.
FIG. 2 is a diagram showing the main part configuration of a dynamic RAM according to an embodiment of the present invention, and FIG. 3 is a diagram showing the specific structure of the address buffer.
4 is a specific circuit diagram of the activation signal distribution circuit, FIG. 5 is a specific circuit diagram of the row decoder, FIG. 6 is a diagram showing the operation timing of the address buffer, and FIG. 7 is a test diagram. FIG. 3 is a diagram for explaining a method of applying an external control signal during operation. 11.12...Memory array block, 21°22.
. . . Row decoder, 31.32 . . . Control circuit, 4 . . . Address buffer, 5 . Applicant's agent Patent attorney Takehiko Suzue Figure 4 Figure 5 Ao A, A2 ------An (Entry 0) Figure 7

Claims (1)

[Claims] In a semiconductor memory device configured such that a memory array divided into a plurality of blocks is integrated and formed on a semiconductor substrate, and any one block is selectively driven by an external address input, the plurality of blocks are selectively driven in response to an external address input. an activation signal distribution circuit for selectively driving one of the blocks, and means for controlling the distribution circuit during an operation test to simultaneously supply activation signals to two or more of the plurality of blocks. A semiconductor memory device characterized by: