JPS63184996A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To measure the same operation margin as a normal mode in a test mode by preventing two or more memory cells belonging to the same external input/output pin from belonging to the same partial memory cell matrix and preventing them from being selected by the same column decoder. CONSTITUTION:A memory cell matrix is divided to M-number or more partial memory cell matrixes, and two or more memory cells MC10 and MC20 of memory cells simultaneously accessed in the test mode are prevented from belonging to the same partial memory cell matrix and from being selected by the same column decoder YDECO with respect to memory cells MC10 and MC20 where data inputted from and outputted to the same external input/output terminals Din and Dout is stored in the normal mode. Thus, the difference between the operation margin measured in the test mode and that in the normal mode is eliminated in case of test circuit layout, and the test time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a test circuit layout with high detection ability.

[Conventional technology]

The storage capacity of semiconductor memory devices continues to rapidly increase by four times every two to three years, and devices with a storage capacity of 1 Mbit or 4 Mbit are now being commercialized. One of the problems that has emerged is the test time. For example, if the storage capacity quadruples, even the simplest test pattern will require four times as much test time.
In order to guarantee high quality, it is necessary to perform a test with a longer pattern length. In other words, in large-capacity semiconductor memory devices, advanced finer patterns are being developed, resulting in an increase in parasitic element effects, while higher operating speeds are also being added, leading to an increase in internally generated noise, and test pattern lengths are increasing. There is a strong tendency to require long and complex tests. In this case, the rate of increase in pattern length is usually much larger than the rate of increase in storage capacity.

An increase in test time is undesirable because it increases manufacturing costs and reduces production capacity.

Therefore, a method called a so-called test circuit has been introduced in response to this problem. For example, IM word x 1
It was devised so that it is possible to test 4 bits of memory at the same time for bit-structured memories, and it appears as if a memory of 256 words x 4 bits is being tested, so the test time is less than that of a 1M bit memory. The idea is that it can be tested in just 256 bits of memory test time.

The conventional general circuit configuration will be explained with reference to FIG.

An example of a DRA MO having an IM word x 1 bit configuration will be described below.

1- The counter electrode of the storage capacitor element of a transistor type memory cell is usually formed by a polycrystalline silicon electrode extending planarly on a silicon substrate via a capacitor gate insulating film, and is shared by a plurality of memory cells. In FIG. 4, 1.2 corresponds to this, and here it will be called a memo cell plate. W.L.I.

WL2 is a word line, usually formed of a polycrystalline silicon dove. In the figure, only one cell is shown on each memory cell plate, but in reality, the number of cells determined by the refresh cycle is arrayed in parallel. Therefore, here, 512 word lines are arranged on each memory cell plate. XDEC1 and XDEC2 are
The row decoder selects and activates one word line from among the word lines on each memory cell plate, and operates according to address information given from the outside.

WLI and WL2 may be considered selected word lines.

D arranged in a direction perpendicular to word lines WLI and WL2
ll, D21, and D22 are data lines, which are usually made of aluminum or polycrystalline silicon. These are paired as Dll, L)12, etc., respectively. At the intersection of the word line and the data line pair, a memory cell is arranged at the intersection with one of the data lines of the data line pair. For example, regarding the word line WL1, the memory cell MC11 is located at the intersection with the data lines Dll and D12.
MC12 is arranged.

One sense amplifier S is connected to the data line pair Dll, Dll.
AI1 is arranged, activated by the sense amplifier activation signal SEI, and generated by a read operation from the memory cell MC11.

5) amplifies the minute potential difference between them. In Figure 4, two data lines and two sense amplifiers are connected on each memory cell grid.
Although only one unit is shown, in reality, each data line pair sense amplifier is 10 units per memory cell plate.
24 pairs of 1024 units are arrayed, and a sense amplifier activation signal SEX is provided.

5E2u, which is commonly wired for each memory cell cell plate. YDEC in the center of FIG. 4 is a column decoder that operates according to an external address signal, selects 4 pairs from 2048 data line pairs on both sides, and selects 4 pairs of I10 bus lines on both sides.
Connect to 00 to l103 and transfer data. Although only one YDEC is shown in FIG. 4, there are actually 512 YDECs in the vertical direction in the figure. The data transferred to the I10 bus is transferred to data amplifiers DAI to DA4.
is amplified. The above is a general layout method when selecting 4 bits from a memory cell array and writing or reading 4 bits of data. In this way, adjacent data line pairs are selected by one YDEC and I1
The method of transferring data to the 0 bus is generally widely used because of its ease of layout and high efficiency in using the surface area of the chip.

When operating as a normal memory with an IM word x 1 bit configuration, one pair is selected from the four pairs of I10 buses (by circuit group 3), and the external input data on the input terminal Din is transferred to the selected one. Write to the pair of I10 buses, or send the signal on the selected pair of L buses to the output terminal Dou.
It will be output to t. On the other hand, test mode command signal T
If you enter 4-bit parallel test mode, -
During 1lF @ write operation, the external input data on the input terminal Din is written to all four pairs of I10 buses, and a certain b
During a read operation, the data appearing on the four pairs of I10 buses are compared and the determination result is output to the output terminal 1) out. This method of determination involves high potential.

Various allocation methods such as low potential and floating are possible, and there are also various methods such as outputting some of the four data to the external address bin without being judged as it is, but it is not important here. Therefore, I will omit it.

The important point is that when mounting a test circuit on a semiconductor memory device, the number of external pins cannot be increased. data, that is, the same data will be written.

[Problem that the invention seeks to solve]

In the layout of the conventional test circuit described above, multiple bits that share a group of conductors constituting a memory cell array, that is, a memory cell plate, a word line, a control signal line, such as a sense amplifier activation signal, etc., are connected to each other during a test mode write operation. However, during normal operation, they are never selected at the same time. In other words, in actual use, various combinations of data are often written into and exposed to these multiple bits;
The test mode has the disadvantage that free data patterns cannot be examined.

Differences in operating margin due to data patterns written in semiconductor memory devices (so-called margin pattern dependence) are largely due to stray coupling capacitance existing in the memory cell array that handles minute signal tubes and noise transmitted via conductor layers. In the case of the test circuit layout as described above, the difference between the operating margin measured in the test mode and the operating margin measured in the normal mode may become large. In this case, measuring only in test mode may lead to a drop in quality, and in the end the operating margin must be confirmed in normal mode, so the effect of reducing test time is very small. turn into.

Furthermore, in the above embodiment, the memory cells mcll, Mc12, MC21,
mc22 is selected by the column decoder YDEC of 1 town, and the determination method in the test mode is often performed by comparing 4-bit read data as described above, and the "a" of the data itself Since "," and "L" are not tested, some failure modes related to column decoders, such as multiple selection of column decoders, may not be detected in the test mode, and similarly, the effect of reducing test time may be reduced.

[Means to solve all problems]

A semiconductor memory device of the present invention has a plurality of words #* arranged in parallel and a plurality of data line groups arranged in parallel in a direction perpendicular to the word lines, and the word line group and the data line A semiconductor memory device that has a memory cell matrix at each intersection with a group, has an N-bit write or read function in a normal mode, and has an MxN bit simultaneous write or read function or a determination function in a test mode. In this case, the memory cell matrix is divided into M or more partial memory cell matrices, and two memory cells storing data input/output to the same external input/output terminal in the normal mode can be accessed simultaneously in the test mode. It is assumed that the memory cells having two or more bits do not belong to the same partial memory cell matrix and are not selected by the same column decoder.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a layout diagram of an embodiment of the present invention, and the notation of symbols and the method of omitting a plurality of symbols are exactly the same as the conventional method shown in FIG.

This point is exactly the same in FIGS. 2 and 3 below.

Further, a memory having an IM word x 1 bit configuration and equipped with a 4-bit parallel test mode will be explained as an example.

In FIG. 1, the memory cell matrix is divided into eight partial memory cell matrixes, each having 256 word lines Fi, 512 sense amplifiers, and 512 pairs of data lines. As in the conventional example, the row decoder
DEC10 selects one word line WLIO, memory cell MCl0 is accessed, and data line pair DIO, DI is selected.
A signal potential difference appears between data lines D10 and D10.Q, and then sense amplifier SAI0 is activated by sense amplifier activation signal 5EIO, and data line pair D10. The DlO signal is m wide. After that, the column decoder YDECO causes the transistor QI to be
O, -Q sl is not in ON state, data line pair D10
The information of ゜f) 10 is transferred to the engineering 10 bus l1010. At this time, I10 selector l10S1 is I10 bus l1
010 is selected and the operation of the circuit group 50 is also the same as that of the fourth conventional example.
The operation is exactly the same as that of circuit group 3 in the figure. All four portions surrounded by dashed lines have the same configuration.

In the 4-bit parallel test mode, the same data is written or read into memory cells of 1 bit each in each of the above-mentioned four blocks inside the dashed line, and a total of 4 pins of memory cells. However, the characteristic point is that even if the same data is written to all four pits, they belong to different partial memory cell matrices, and at least within each partial memory cell matrix,
It is possible to store any data pattern that is exactly the same as during normal operation, and the 4-bit memory cells are selected by different column decoders.

Therefore, it is possible to accurately measure the pattern dependence of the operating margin even in the test mode in IJ boxes (in IJs that share word lines, memory cell rates, and control signals), and vice versa. As for the cell matrices, for example, the word line has a row decoder, word M&drive circuit, and word line WLIQ, which have completely independent configurations.

WL20, WL30, and WL40 are activated at the same timing, but they are not connected and conductive to each other.
Sense amplifier activation signal SEI o, 5E20.5
E30,5E40 and memory cell rate 10.20,3
The same applies to 0.40.

Therefore, since the noise effect due to mutual data interference between partial memory cell matrices is extremely small, the difference in operating margin between normal operation and test mode can be kept small. Furthermore, since all four bits are selected by different column decoders, there is no deterioration in detection ability as described above.

In other words, even in test mode, the only important point is that there are no more than two memory cells in the partial memory cell matrix that are accessed at the same time, and that the same column decoder never selects two or more bits to be tested at the same time. , various variants are possible.

For example, the position of the decoder and the sense amplifier can be freely arranged within the partial memory matrix, and the sense amplifier may be a shared sense amplifier.

Although FIG. 1 shows an example of a folded data line arrangement, FIG. 3 shows an example in which each partial memory cell matrix is arranged as an open data line. Inside the dashed line is
It is assumed that all blocks are the same.

Furthermore, even if the structure is divided into more partial memory cell matrices in the example 2 of FIG. The effect remains the same.

Furthermore, even if the layout of one pair of I10 buses per partial memory cell matrix in FIG. 1 is not preferable, two pairs of I10 buses can be arranged in each partial memory cell matrix as shown in FIG. A method can be adopted in which a pair is selected by an I10 selection circuit l1010 outside the array.

Furthermore, a switch is provided at the output of the column decoder, and ys
There is also a method in which one of the I10 buses is disconnected without operating at all by controlling wo and YSWlt separately.

The above has described an example of an IM word x 1 bit m-structured memory, but an analogy can also be easily made for an XN-bit structure.
For example, it can be seen that memory cells accessed simultaneously in the test mode may belong to the same partial memory cell matrix as long as they belong to different external I10 bins.

〔Effect of the invention〕

As detailed in the previous section, two or more memory cells that belong to the same external 1I10 pin belong to the same partial memory cell matrix in memory cells that are divided into partial memory cell matrices and accessed simultaneously in the test mode. In test mode, it is possible to measure the operating margin in the same way as in normal mode. This makes it possible to maintain high quality.

[Brief explanation of the drawing]

Fig. 1 shows an example of the present invention implemented, Fig. 2 shows another embodiment of the invention, Fig. 3 shows an example in which the example of Fig. 1 is realized using another layout method, and Fig. 4 shows a conventional example. It is a layout diagram showing an example. 1.2, L O, 20, 100, 200, 110, 1
20...1-Electrode plate of each quantum element counter electrode of transistor memory cell, WLi...Word H
1Di, Di... Data line, MCi...
・Memory cell, XDECi...Row decoder, S
Ai...Sense amplifier, SEi...Sense amplifier activation signal, YDEC...Column decoder, Engineering 10i...I10 bus, Qi...
・Switching transistor between data amplifier and engineering 10 bus, DAi...data amplifier, l10Si...
...I10 selector, TE-...Test mode command signal, Din...External data input terminal, D
out... each indicates an external data output terminal.

Claims (1)

[Claims] It has a plurality of word line groups arranged in parallel and a plurality of data line groups arranged in parallel in a direction perpendicular to the word lines, and a memory is provided at each intersection of the word line group and the data line group. In a semiconductor memory device that has a memory cell matrix in which cells are arranged, has a write or read function for N bits at the same time in a normal mode, and has a write or read function or a judgment function for MXM bits at the same time in a test mode. , the memory cell matrix is divided into M or more partial memory cell matrices, and among the memory cells that store data input and output from the same external input/output terminal in the normal mode, the memory cells are simultaneously accessed in the test mode. A semiconductor memory device characterized in that memory cells of two or more bits do not belong to the same partial memory cell matrix and are not selected by the same column decoder.