JP2772640B2 - Semiconductor storage device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device having a high yield.

[Prior art] In recent years, in order to respond to the demand for microelectronics of industrial and consumer equipment, LSI (Large Scale Integrated Circuit)
VLSIs (ultra large scale integrated circuits), which have been further scaled up, have been developed and are commercially available.

In such a VLSI, it is necessary to integrate millions of elements on one silicon chip, and therefore, a fine processing technology with a minimum dimension of about 1 μm is used. For this reason,
Foreign matter with a particle size of 1 μm or less, which was not a problem in the past,
Residues of various materials for processing adversely affect the device, and the yield of non-defective products, that is, the yield is significantly reduced.

Therefore, in order to improve the yield, a redundant circuit technology is generally adopted. In this method, a spare (spare) word line or bit line is provided on the same chip, and when there is a defective cell in the memory cell array, the defective cell is replaced with a spare line in word or bit line units. is there. As a result, most of the chips that should be removed as defectives are relieved by employing such a redundant circuit, so that the yield can be greatly improved.

FIG. 3 is a block diagram showing a conventional 1M (mega) bit dynamic RAM (Random Access Memory) having a redundant circuit. In this figure, a portion relating to a redundant circuit is omitted for simplification, but this will be described later.

With reference to FIG. 3, the dynamic RAM is four and to memory arrays 1 are divided into blocks 4, word for generating a signal W _DS for driving the word lines contained to 4 each memory no array 1 Line drive signal generation circuit 51
When, and a word line boost circuit 10 for boosting the word line drive signal W _DS. Word line drive signal generation circuit
Reference numeral 51 is connected to receive a ▲ ▼ (row address strobe) signal via a RAS buffer 52. In each of the memory arrays 1 to 4, for example, the memory array 1, a row decoder 1a, a sense amplifier 1b, and a column decoder 1c are connected.

In this dynamic RAM, four blocks of memory arrays 1 to 4 are accessed in a 4-bit high-speed serial access mode called a nibble mode.

 Next, the operation will be described.

In general, a dynamic RAM receives row and column address signals in a time sharing manner through terminals A0 to A9. First, each address signal is input at the edge timing when the ▲ ▼ signal and ▲ ▼ (column address strobe) signal fall. Next, one of the four row decoders is selected by the row address signal, and the word line is activated by the boosted word line drive signal _WDB . On the other hand, one of the four column decoders is selected by the column address signal, and the bit line is selected. Thereby, for example, a signal stored in a memory cell is applied to a bit line during a read operation.

FIG. 4 is a circuit diagram showing an equivalent circuit of one conventional memory cell.

Referring to Figure 4, the memory cell MC includes a transistor Q _M for switching connected to the word line WL and bit line BL, and a capacitor C _S. By applying a voltage of high level (1) or low (0) to the capacitor C _S, the signal is stored.

Voltage V _CP of a certain level to one electrode of the capacitor C _S
Is given. When the word line WL is activated transistor Q _M is turned on. Accordingly, the bit line charge stored in the capacitor C _S is brought to a floating state
Given to BL. Here, the stray capacitance C _BL of the bit line BL because the 10 times the magnitude of the capacitance of the capacitor C _S, appear only a few hundred mV of potential change in the bit line BL.

Therefore, as shown in FIG.
After being amplified by the sense amplifier, it is supplied to a read / write I / O line. This signal is further amplified by a preamplifier.

By the above series of operations, the 4-bit signals of the memory cells MC1 to MC4 specified in the memory arrays 1 to 4 are simultaneously transmitted to the preamplifiers 21 to 24 via the I / O lines.
Given to.

In the nibble mode, the nibble decoder 58 operates as a shift register, and sequentially transfers these 4-bit signals to the output buffer 57 at high speed by toggling of the CAS signal. On the other hand, in the normal mode, nibble decoder 58 operates as a decoder for decoding top row and column address signals RA9 and CA9, and sets address signals RA9 and CA9.
, A 1-bit signal of the 4-bit signal is transferred to the output buffer 57.

On the other hand, in the write operation, the input data input via the input buffer 56 is written to the memory cells MC1 to MC4 via the I / O lines.

 Next, the word line boost circuit will be described.

Referring to Figure 4 again, when the word line WL is changed to a high level, the transistor Q _M is turned on. _Assuming that this high level is the power supply voltage level Vcc, the storage level higher by the threshold voltage _VTH of the transistor _QM is lost. This loss rate is usually about 20%, and does not cause a malfunction immediately. However, for example, when the power supply voltage level is lowered, there is a problem that the loss is relatively increased and the operation margin is reduced. The word line boost circuit
The problem intended to solve, the voltage level of the word line is intended to boost the power supply voltage level Vcc over a value obtained by adding the threshold voltage V _TH of the transistor Q _M.

FIG. 5 is a circuit diagram showing an example of a conventional word line boost circuit.

Referring to FIG. 5, this word line boost circuit 10
Inverter 41 connected to receive word line drive signal _WDS , and a clocked inverter connected to its output
Includes a 42, a series connection of the inverter 43 to 46 for the connected delay the output of the clocked inverter 42, and a capacitor C _B for the boost. Node N _F of the inverter 44 and 45 are connected is connected to the clock input of the clocked inverter 42. Incidentally, the node N _B denotes the output of the inverter 46, W _DB denotes a boosted word line driving signal.

FIG. 6 is a timing chart for explaining the operation of the word line boost circuit shown in FIG.

Next, the operation of the word line boost circuit 10 will be described with reference to FIG. 5 and FIG.

First, the word line drive signal W _DS is changed to the high level at time T _0. Output signal W _DB is _supplied to inverters 41 and 42
It changes to high level at time T ₁ and delayed by. Further, the voltage level V _NF node N _F is changed to the high level at time T _2, delayed by the inverter 43 and 44. The clocked inverter 42 uses this high level voltage V _NF
And the output of clocked inverter 42 (the output of word line boost circuit 10) is brought into a floating state having power supply voltage level Vcc.

Thereafter, further, the voltage level V _NB Node N _B is changed to the high level at time T ₃ by the delay of the inverters 45 and 46. Accordingly, the voltage level of the output signal W _DB is boosted to the level Vcc + V.alpha exceeding the power supply voltage level Vcc by the capacitive coupling of the capacitor C _B. By setting the capacitance value of the capacitor C _B appropriate, to the Vα equal to or higher than the threshold voltage V _TH of the transistor Q _M.

In this way, the word line drive signal _WDS is boosted, and the boosted word line drive signal _WDB is obtained.The high level of the signal _WDB is disconnected from the power supply and becomes a floating state. Output from the output.

The boosted word line drive signal _WDB is applied to memory arrays 1 to 4 via four row decoders as shown in FIG.
Activate WL at the same time.

FIG. 7 is a schematic circuit diagram showing an example of a conventional row decoder. In this figure, as an example, the row decoder 1a of FIG.
Is shown.

Referring to FIG. 7, each of the row decoders 1a
It includes 512 unit row decoders RD for activating one of the 512 rows.
RD _K and its adjacent (K + 1) th unit row decoder RD _{K + 1}
Is shown. For example, the K-th unit row decoder RD
_K comprises a NAND gate 71 connected to receive row address signals RA0 through RA8, an inverter 72 connected to its output, three N-channel transistors Q _AK , Q _BK and
Includes Q _CK .

In operation, for example when it is selected the unit row decoder RD _K, to no row address signals RA0 becomes RA8 all high level, NAND gate 71 outputs a low level signal. This signal is inverted is supplied to the gate of the transistor Q _BK by the inverter 72, also the transistor Q _CK
Is also given to the gate. This allows the transistor Q
_BK is turned on, a boosted word line driving signal W _DB is applied to the word line WL _K via the transistor Q _BK.

On the other hand, in the adjacent unit row decoder RD _{K + 1} , the NAND gate outputs a high-level signal because of the non-selection state, so that the transistor Q _{BK + 1} turns off and the transistor Q _{CK + 1}
Turns on. This brings word line WL _{K + 1} to a low level.

 Next, a redundant circuit will be described.

FIG. 8 is a conceptual diagram showing a conventional memory array and a redundant circuit provided therein.

Referring to FIG. 8, a spare row decoder 1as provided in row decoder 1a and a spare row 1s provided in memory array 1 and having a plurality of spare memory cells are provided here as redundant circuits. Are provided. Generally, a spare column decoder and a spare column are further provided, but are omitted in this figure.

When a defect is found in a certain memory cell or word line in the memory array 1 by the redundancy test, a unit row decoder for activating the word line is always inactivated, and the defective unit row decoder , The spare row decoder 1as is programmed so as to be selected when an address signal for selecting. Generally, this program is performed by blowing the fuse element with a high voltage pulse or a laser beam. Thus, the row containing the defect is replaced with the spare row 1s, and the defective product is reproduced as a good product.

[Problem to be Solved by the Invention] FIG. 9 is a circuit diagram showing a case where the row decoder shown in FIG. 7 has an abnormality.

Referring to FIG. 9, FIG. 9 shows, as an example of an abnormality, a case where adjacent two word lines WL _K and WL _{K + 1} are short-circuited by a foreign substance having resistance R _S. This allows
The boosted word line drive signal _WDB flows to the ground via a resistor _RS in a path indicated by an arrow. As described above, since this signal _WDB is output from the word line boost circuit whose output is brought into a floating state, the signal WDB
Level _DB decreases, the word line WL _K becomes poor.

However, as shown in FIG. 3, the signal W _DB 4
Since four word lines WL are simultaneously applied to four word decoders via one row decoder, the level of signal _WDB is reduced even if only the word line of memory array 1 causes such a defect. Are also determined to be defective. That is, these are regarded as defective even though the other word lines have no defect.

Thus, if only one spare row decoder and one spare row are provided in each of memory arrays 1 to 4, all of them are used for replacement of word lines, and there is a defect in memory cells. When it exists, there is a problem that the yield cannot be reduced because it cannot be remedied. Further, the spare row decoder and the spare row have two spare rows.
Even if more than one are prepared, there is also a problem that they cannot be used effectively because of the apparent defects described above.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a semiconductor memory device that can obtain a high yield by effectively taking measures even if a defect exists.

[Means for Solving the Problems] A semiconductor memory device according to the invention of claim (1) is provided with a plurality of memory cell array blocks each including a plurality of memory cells connected to a plurality of word lines, and a state input from outside. A driving voltage generating means for generating a driving voltage for driving a word line in response to a state control signal provided through the means and an address signal provided through the address input means; A block selection signal input means for receiving a block selection signal indicating which drive voltage is to be applied from the outside, and a drive voltage generation means connected between the drive voltage generation means and the plurality of memory cell array blocks; Drive voltage distribution means for supplying one of the plurality of memory cell array blocks.

According to a second aspect of the present invention, there is provided a semiconductor memory device, comprising: a plurality of memory cell array blocks each including a plurality of memory cells connected to a plurality of word lines; and a state control provided from outside via state input means. Drive voltage generating means for generating a first drive voltage for driving a word line in response to a signal and an address signal provided via address input means, and a second drive voltage for driving the word line A switching signal inputting means for externally receiving a switching signal for selecting which of the first and second drive voltages is to be applied to the memory cell array block;
A drive voltage generation unit, a power supply unit, and a switching unit that is connected between the plurality of memory cell array blocks and connects one of the drive voltage generation unit and the power supply unit to the plurality of memory cell array blocks in response to a switching signal. Including.

[Operation] In the semiconductor memory device according to the invention of claim (1), the drive voltage distribution means applies the drive voltage from the drive voltage generation means to the memory cell array block selected by the block selection signal among the plurality of memory cell array blocks. .
As a result, it is possible to know the location where the defect is present for each memory cell array block. Therefore,
Effective measures can be taken, for example, by applying a redundant circuit.

In the semiconductor memory device according to the invention of claim (2), the switching means connects one of the driving voltage generating means or the power supply means selected by the switching signal to the plurality of memory cell array blocks. Further, when the power supply is connected to the plurality of memory cell array blocks, the switching means applies the second voltage to the plurality of memory cell array blocks in response to the state signal and the address signal. As a result, the word lines of the memory cell array block are driven by the power supply means, so that a drop in the word line drive voltage caused by a defect existing in one memory cell array block does not affect the other memory cell array blocks. The location where the defect exists can be known for each memory cell array block. Therefore, effective measures can be taken, for example, by applying a redundant circuit.

[Embodiment of the Invention] FIG. 1A is a block diagram showing a 1-Mbit dynamic RAM according to an embodiment of the present invention.

Referring to FIG. 1A, the difference between this dynamic RAM and the conventional one shown in FIG. 3 is that a distribution circuit 80 is provided between word line boost circuit 10 and each row decoder. That is, a test signal generation circuit 90 for controlling this is provided outside. That is, the distribution circuit
80 selectively supplies boosted word line drive signal _WDB to each row decoder in response to control signals φs, BS0 and BS1 from test signal generation circuit 90 applied via the spare pad.

FIG. 2A is a circuit diagram showing an example of the distribution circuit used in FIG. 1A.

Referring to Figure 2A, the distribution circuit, selectively outputs a decoder 81 for decoding the block select signals BS0 and BS1, and in response to the switching control signal φs boosted word line driving signal W _DB And a switching circuit 82 that performs switching. The decoder 81 includes AND gates 811 to 814 and inverters 815 and 816. Switching circuit 82 is, for example, connected to a NOR gate 821 connected to receive an output signal from decoder 81 and a switching control signal φs for a portion outputting word line drive signal _WDB1 to memory array 1, and to an output thereof. Inverter 822 and N-channel transistors Q ₁₀ , Q ₂₀ and Q ₃₀ connected to these outputs. Further, a resistor 820 is connected between the signal line L connected to receive the switching control signal φs and the power supply Vcc.

 Next, the operation will be described.

First, in a test operation such as a redundancy test,
For example, a case where a high-level word line drive signal _WDB1 is output only to memory array 1 will be described.

A low-level block selection signal BS0 and BS1 and a low-level switching control signal φs are supplied from a test signal generation circuit 90 provided outside. AND gate 811 outputs signal BS0
And outputs a high-level signal in response to BS1. On the other hand, the other AND gates 812 to 814 output low level signals. Therefore, only the NOR gate 821 outputs a low-level signal, and the other NOR gates output a high-level signal.

Thus, the transistor Q ₁₀ and the transistor Q ₂₁
To Q ₂₃ is turned on, to the transistors Q ₂₀ and the transistor Q ₁₁ Q ₁₃ is turned off. Therefore, it boosted word line driving signal W _DB are outputted as the word line drive signal W _DB1 via the transistor Q _10. On the other hand, the other memory arrays 2 to 4 have the word line drive signal W at the ground level.
_DB2 to W _DB4 are output.

Similarly, by giving to select the level of the block select signals BS0 and BS1 appropriate, to the drive signal W no _DB2 other word lines for each well of W _DB4, it is possible to output a high level signal.

Next, when the dynamic RAM performs a normal operation, a terminal (spare pad) receiving the switching control signal φs from the outside is opened. At this time, the signal line L to receive the switching control signal φs is pulled up to a high level by the power supply Vcc connected via the resistor 820. As a result, all the NOR gates receive the block selection signal BS0 and
Regardless BS1 level and outputs a high level signal, to the transistors Q ₁₀ Q ₁₃ is turned on. Therefore, boosted word line driving signal W _DB are to _DB1 no respective word line drive signal W through Q ₁₃ to the transistors Q ₁₀ are outputted simultaneously as W _DB4.

As described above, in the test operation, the word line drive signals W _DB1 to W _DB4 are selectively provided for each of the memory arrays 1 to _4.
Therefore, for example, even when a short circuit due to a foreign substance occurs between word lines as shown in FIG. 9, it is possible to limitly know that the defect exists in memory array 1. The spare row decoder can be used only for the memory array 1 in which a defect actually exists. Therefore, spare row decoders provided in memory arrays 2 to 4 can be used more effectively, for example, for repairing other defects such as memory cells.
The yield can be improved.

In the test operation described above, the operation in the nibble mode cannot be performed. However, there is no problem in performing the nibble mode operation in, for example, a redundancy test.

FIG. 1B is a block diagram showing a 1-Mbit dynamic RAM according to an embodiment of the present invention.

Referring to Figure 1B, obtained by different points compared with the ones the dynamic RAM and the conventional shown in Figure 3 is that the word line boosting circuit 15 boosts the word line drive signal W _DS And a function of switching and outputting a given signal and a voltage signal _VWL provided by an external power supply. Note that a test signal generation circuit 90 is provided outside, from which an external voltage signal _VWL and a switching control signal S1 are supplied to the dynamic RAM.

FIG. 2B is a circuit diagram showing an example of a word line boost circuit having a switching function used in the dynamic RAM shown in FIG. 1B.

Referring to FIG. 2B, the word line boosting circuit 15 having the switching function further includes a word line driving signal _WDS and an external voltage signal _{VWL in} comparison with the conventional circuit shown in FIG. Switches SW1 and SW2 connected to switch between
If, and an N-channel transistor Q ₁ and Q ₂ connected as to output the external voltage signal V _WL in response to a signal W _DS.

FIG. 2C is a timing chart for explaining the operation of the word line boost circuit having the switching function shown in FIG. 2B.

Next, the operation will be described with reference to FIGS. 2B and 2C.

First, in a normal operation, the switch SW1 is connected to the terminal a, and the switch SW2 is connected to the terminal c. Therefore, the word line boost circuit 15
The same operation as the conventional one shown in the figure is performed.

Next, in a test operation such as a redundancy test, the changeover switches SW1 and SW2 are connected to the terminals b and d in response to the switch control signal S1, respectively. The external voltage signal V _WL is applied to the transistor Q _2.

When the word line drive signal W _DS is changed to the high level at time T _0, the node N voltage V _NA of _A rose Vcc-V _TH2 (V _TH2
Become is the threshold voltage of the transistor Q _1). The output signal W _DB is changed to the high level at time T ₁ is delayed by the inverter 41 and 42. Further, the voltage level V _NF node N _F is changed to the high level at time T _2, delayed by the inverter 43 and 44. Clocked inverter 42 is cut off by this high level voltage _VNF , and the output of clocked inverter 42 is brought into a floating state.

Thereafter, further, the voltage level V _NB Node N _B is changed to the high level at time T ₃ by the delay of the inverters 45 and 46. Accordingly, the voltage level V _NA of the node N _A is boosted to Vcc + V? Due to the capacitive coupling of the capacitor C _B.
Here, the capacitor C _B, by the node N _A is suitably setting the ratio of the stray capacitance C _NA with between the ground level of the output signal W _{DB is, Vcc + Vβ ≧ V WL +} W TH3 (V TH3 it can satisfy the relation of the threshold voltage of Torajisuta Q _2). At this time, the transistor Q ₂ is completely turned on,
Level of the output signal W _DB is clamped at the level of the external voltage signal V _WL.

By using an external power supply having a low impedance, for example, even if a short circuit due to foreign matter occurs in the word line as shown in FIG.
Extremely low levels of W _DB can be prevented. Therefore, another memory array 2 selected at the same time
No. to 4 word lines are not regarded as defective, and the spare row decoders provided in these memory arrays 2 to 4 can be used more effectively, such as for repairing defects of other memory cells, and so on, so that the yield is increased. Can be improved.

In the two embodiments described above, the control signal is:
It is provided externally via a dedicated pad provided exclusively, but it is generated internally using other externally applied signals, for example, changing timing of RAS signal and CAS signal. A configuration may be adopted.

Alternatively, a configuration may be adopted in which a signal having a specific level different from that level is applied to a terminal to which a predetermined voltage level is to be externally applied, and this is detected to generate a control signal internally.

Further, in these embodiments, a dynamic semiconductor memory device using an N-channel memory cell has been described, but these inventions can also be applied to a dynamic semiconductor memory device using a P-channel memory cell. In that case, a circuit for boosting to a potential lower than the ground potential may be provided as a word line boost circuit. At this time, it is necessary to _{apply a} voltage signal _VWL lower than the ground level.

[Effects of the Invention] As described above, according to the invention of claim (1), the drive voltage from the drive voltage generating means in response to an externally applied block selection signal is output from the plurality of memory cell array blocks. Since the driving voltage distribution means for one is included, it is possible to know the location where the defect exists by limiting it for each memory cell array block. By taking effective measures such as applying a redundant circuit, a high yield can be obtained. A semiconductor memory device can be obtained.

According to the invention of claim (2), since switching means for connecting the power supply means to the plurality of memory cell array blocks in place of the normal drive voltage generation means in response to the switching signal given from the outside is included, It is possible to know the location where the defect exists for each memory cell array block, and it is possible to obtain a semiconductor memory device with a high yield by taking effective measures such as applying a redundant circuit.

[Brief description of the drawings]

FIG. 1A is a block diagram showing a 1 Mbit dynamic RAM according to an embodiment of the present invention. FIG. 1B is a block diagram showing a 1-Mbit dynamic RAM according to an embodiment of the present invention. FIG.
FIG. 3 is a circuit diagram illustrating an example of a distribution circuit used in the dynamic RAM illustrated in FIG. FIG. 2B is a circuit diagram showing an example of a word line boost circuit having a switching function used in the dynamic RAM shown in FIG. 1B. Figure 2C
FIG. 3B is a timing chart for explaining the operation of the word line boost circuit having the switching function shown in FIG. 2B. FIG. 3 is a block diagram showing a conventional 1 Mbit dynamic RAM. FIG. 4 is a circuit diagram showing an equivalent circuit of a conventional memory cell. FIG. 5 is a circuit diagram showing an example of a conventional word line boost circuit. FIG. 6 is a timing chart for explaining the operation of the word line boost circuit shown in FIG. FIG. 7 is a schematic circuit diagram showing an example of a conventional row decoder. FIG. 8 is a conceptual diagram showing a conventional memory array and a redundant circuit provided therein. FIG. 9 is a circuit diagram showing a case where the row decoder shown in FIG. 7 has an abnormality. In the figure, 1 to 4 are memory arrays, 1a is a row decoder, 1b is a sense amplifier, 1c is a column decoder, 1as is a spare row decoder, 1s is a spare row, 10 and 15 are word line boost circuits, and 51 is a word line drive. Signal generation circuit, 80 is a distribution circuit,
81 is a decoder, 82 is a switching circuit, and 90 is a test signal generation circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hiroyuki Yamazaki 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation LSI Research Institute (56) References JP-A 1-235099 (JP, A JP-A-1-264700 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 11/407

Claims (2)

(57) [Claims] 1. A semiconductor memory device comprising a plurality of memory cell array blocks each including a plurality of memory cells connected to a plurality of word lines, wherein a state control for externally controlling a state of the storage device is provided. State input means for receiving a signal; address input means for receiving an address signal for externally addressing the storage device; responsive to a state signal from the state input means and an address signal from the address input means, Drive voltage generation means for generating a drive voltage for driving a word line of a memory cell array block; and a block selection signal for indicating to which of the plurality of memory cell array blocks the drive voltage from the drive voltage generation means is applied. Block selection signal input means for receiving the external A switching signal input unit for receiving a switching signal for switching from outside, a switching signal connected between the drive voltage generating unit and the plurality of memory cell array blocks, and a switching signal externally supplied through the switching signal input unit and the block. In response to a block selection signal externally applied through a selection signal input means, a drive voltage from the drive voltage generation means is applied to one of the plurality of memory cell array blocks in a test mode. And a drive voltage distributing means for applying to all the memory cell array blocks in the normal mode. 2. A semiconductor memory device having a plurality of memory cell array blocks each including a plurality of memory cells connected to a plurality of word lines, wherein a state control for externally controlling a state of the storage device is provided. State input means for receiving a signal; address input means for receiving an address signal for externally addressing the storage device; responsive to a state signal from the state input means and an address signal from the address input means, A drive voltage generating means for generating a first drive voltage for driving a word line of the memory cell array block; a power supply means for outputting a second drive voltage for driving a word line of the memory cell array block; Which of the first and second drive voltages is applied to the plurality of memory cell array blocks is selected. A switching signal input unit for receiving a switching signal from the outside; a switching signal input unit connected between the drive voltage generation unit and the power supply unit and the plurality of memory cell array blocks; Responsively includes switching means for connecting any one of the drive voltage generating means or the power supply means to the plurality of memory cell array blocks, wherein the switching means comprises: the power supply means and the plurality of memory cell array blocks; And a second voltage is applied to the plurality of memory cell array blocks in response to a state signal from the state input unit and an address signal from the address input unit when is connected.