JPS60205581A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display device used when displaying images such as characters and graphics from a so-called microcomputer on a CRT display device.

Background Art and Problems When displaying images such as characters and figures from a so-called microcomputer on a CRT display device, data from a central processing unit (CPU) is output using a video random access memory (V-RAM). This V-RAM is read out with a read address associated with the synchronization signal to form a video signal.

Figure 1 shows an example of a device for this purpose, in which the horizontal synchronization signal (H) from the synchronization signal generation circuit +1) is transmitted to the phase detector (
2), and this detection output is sent to a low-pass filter (3).
) through variable frequency oscillation! il (VCO) (4)
supplied to A signal with a frequency corresponding to the pixel clock for reading from the memory, which will be described later, is formed from this V CO (41). This signal is supplied to the 1/8 frequency divider circuit (5) to display each character and figure display block. A frequency-divided clock corresponding to is formed, and a signal of
An address signal is formed that corresponds to a position on the inner surface of the l frame. Further, a signal corresponding to the horizontal synchronization signal is formed in the control circuit (6), and this signal is supplied to the phase detector (2) to perform so-called phase locking. Furthermore, the vertical synchronization signal (V) from the generation circuit (1) is applied to the control circuit (6).
) is supplied to the reset terminal of the

Also, the central processing circuit (CPU) of a microcomputer (
7) The data signals of displayed characters and displayed figures etc. from V-
The RAM (supplied to 81 and written to a desired address, V-RAM+8) is read out by an address signal from the control circuit (6).

The read data is supplied to a video signal conversion circuit (9), and a pixel clock from the VCO (41) is supplied to this conversion circuit (9) to form a video signal.

In this way, video signals such as characters and graphics are formed.

By the way, in the above-mentioned display, it is required to sequentially move (scroll) the displayed characters, figures, etc. in the horizontal direction. Therefore, in the above-mentioned device, the conversion circuit (9
) is supplied to the shift register (1 (I), this shift register Ql is driven by the pixel clock from V CO (41), and the output of each stage of this shift register α is supplied to the selector (11), This selector (11
) is selected by a signal from CPU (71), and the output of any stage is taken out to the output terminal (12).

According to this, a signal whose phase is arbitrarily shifted is extracted by selection of the selector (11), and horizontal scrolling can be performed by controlling this selection.

If the display is monochrome, the display data per pixel is 1
Only bits. Therefore, in the above device, the phase shift means by the shift register OI and the selector (11) is 1
All you need is a pair.

However, when performing color display, one pixel is provided with a plurality of predetermined bits, and for example, 3 bits allow display of 23=8 colors. If the above-mentioned device is applied in this case, three sets of phase shift means of a shift register and a selector must be provided, making the configuration complicated. Furthermore, in the case of displaying 2''-250 colors with 8 bits, 8 sets of phase shift means are required, which is extremely difficult to realize.

Depart! Purpose of J In view of these points, the present invention is intended to provide an excellent quick and easy call display with a simple configuration.

SUMMARY OF THE INVENTION The present invention provides an I! ! In a display device that divides the IA clock to form a signal corresponding to the front block, the synchronization signal and the signal corresponding to the display block are compared in phase, and when the phases of the two do not match, the synchronization signal is used. A display device characterized in that a means for resetting the frequency division and shifting the phase of at least one of the inputs of the phase comparison is provided so that the display block can be scrolled arbitrarily, According to this, good scrolling display can be performed with a simple configuration.

Embodiment In FIG. 2, a horizontal synchronizing signal from a generating circuit (1) is supplied to a shift register (21), and this shift register (21) is driven by a raw clock from V CO (41). The output of each stage of this shift register (21) is supplied to a selector (22), and this selector (22) is selected by a signal from the CPU (7).The signal from this selector (22) is used for phase comparison. Vessel (23
). Further, a signal corresponding to the display block from the control circuit (6) is supplied to the comparator (23). When the phases of the two inputs of the °C comparator (23) do not match, the signal from the selector (22) is taken out and supplied to the reset terminal of the frequency divider circuit (5).

In this device, the horizontal synchronizing signal is phase-shifted and the reset timing of the frequency divider circuit (5) is phase-shifted, so that the timing of the display block is phase-shifted. As a result, the timing of generation of successive addresses in the control circuit (6) is phase-shifted, the formation of signals such as characters and figures to be displayed is phase-shifted, and the display position on the meat surface is horizontally scrolled.

Therefore, in this device, since the generation of the read address itself is phase-shifted, no matter how many bits there are in this address, each bit is simultaneously phase-shifted, and there is no need to provide a phase-shifting means for each bit.

By the way, in the above-mentioned device, the general-purpose control circuit (6) has a built-in final 1/2 frequency divider circuit, and an external frequency divider circuit (
5), 1/4 frequency division is performed. Therefore, from the internal elementary clock as shown in Fig. 3A, a 1/4 frequency divided signal as shown in Fig. 3B is formed, and the frequency is further divided into 1/2 as shown in the box in Fig. 3C. When forming a divided clock corresponding to a block, if the horizontal synchronization signal shown in Figure 3 is delayed (phase shifted) as shown in a, the 1/4 frequency division is reset. However, the subsequent 1/2 frequency division is reset at the same time, or the next 1/4
The signal that is reset by the frequency division signal (C' in FIG. 3) becomes undefined. Therefore, the position of the display block is shifted by 1/2 block, and the display on the screen is disturbed.

On the other hand, in the device described above in ``, the phase of the signal corresponding to the display block and the delayed signal of the horizontal synchronization signal is compared, and if they do not match, a reset is performed.
', the reset is performed again with the next horizontal synchronization signal. Here, the reset is performed only when there is a mismatch, so
It becomes stable when the phases match.

In this way, the display of characters, figures, etc. is scrolled, but according to the above-mentioned device, by simply providing one set of phase shifting means such as a shift register and selector, a plurality of bits and sevens can be scrolled.
It is possible to phase shift the color table at the same time, making it easy to horizontally scroll the color table board row by row.

In the above-mentioned device, the phase shift means of the shift register (21) and the selector (22) is controlled by the control circuit 1! It may be provided on the side of the signal corresponding to the display block from R(6).

Application Example Furthermore, the above-mentioned device is a device that is equipped with two V-RAMs, writes character and graphic data independently, and displays the signals read out in a superimposed manner. It can also be applied to ensure that characters are displayed in the appropriate position.

In FIG. 4, character data from CPU (7) is written to V-RAM (8G), and figure (graphics) data is written to V-RAM (8G) 4.
: m is included. This V-RAM (8C).

(8G) is read out using the read address from the control circuit (6G) and (6G), and an image (No. 4) is formed in the conversion circuit (9G) and (9G), mixed in the mixing circuit (31) and output terminal. It is taken out at (12).

Here, characters are displayed using a 6-pixel clock for each display block, and graphics are displayed using an 8-pixel clock for each display block. Sogo ■ The # base lock from C0 (4) is frequency-divided by the 1/3 frequency divider circuit (5C) and supplied to the control circuit (6C), and the 1/4 frequency divider hJIM (
The frequency is divided by the 5G circuit and supplied to the control circuit 11 (6G circuit).The control circuits (6C) and (6G) have a built-in 1/2 frequency divider circuit.

A horizontal synchronizing signal is directly supplied to the reset terminal of the frequency dividing circuit (5C), and a signal from the comparator (23) is supplied to the reset terminal of the frequency dividing circuit (5G). Further, a vertical synchronization signal is supplied to the reset terminal of the control circuit (6G) through the phase shift circuit (32).

Therefore, in this device, while the characters are displayed fixedly, the figures are shifted vertically and horizontally, and the position of the figures is as small as 1 g!
! The text will now appear in the correct position.

Effects of the Invention According to the present invention, it has become possible to perform good scrolling display with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a conventional device, FIG. 2 is a block diagram of an example of the present invention, FIG. 3 is a diagram for explaining the same, and FIG. 4 is a block diagram of another example. (17 is a synchronization generator circuit, 15) is a frequency divider circuit, (6) is a control circuit, (8) is a V-RAM, (21) is a shift register, (22) is a selector, and (23) is a phase comparator. be.

Claims (1)

[Claims] l! In a display device which divides the Il elementary clock to form a signal corresponding to the 'C table block, the synchronization signal and the signal corresponding to the display block are compared in phase,
When the phases of the two do not match, the synchronization (No. 6) resets the frequency division and provides means for shifting the phase of at least one of the inputs of the phase comparison so that the display block can be scrolled arbitrarily. A display device characterized by: