JPS60205487A - Display control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Technical field] TECHNICAL FIELD The present invention relates to improvements in display control for:

[Seshiba Technology] FIG. 1 shows a block diagram of a conventional color graphics display device.

In the figure, a CPU (microprocessor) 1 is provided that controls the entire device, and a main memory 2 and a display control circuit 3 are connected to this CPU 1. There is a device that holds data, display control circuit 3
controls the color graphics display.

In addition, 71j 4 is the V that holds the γ-column for CRT display.
RAM (video memory), reference numeral 5 is a CRT (video memory) unit.

FIG. 2 shows the display 1 shown in FIG. An example of the II control circuit 3 is shown in a block diagram.

The clock R1 (the = sign is a digit) obtained by the timing controller 11 is input to a counter 12 having a J counter, a line counter, and a row counter. A CRT display synchronization signal qJ is generated from this counter 12 via a display timing circuit 13. On the other hand, a display address is created by the counter 12, and output as a VIt88 address via the multiplexer 15.

Is the read data for display access from VRAM4 a buffer? The signal is input to the video f'A output control circuit 20 via the signal line 19, and a CRT video A signal is generated.

On the other hand, when CPU1 accesses VRAM4, VR
AM4 7 address to V RAM M address register 14
Set to . Then, when the write strobe is input to the CPU interface controller 18, a J: signal is sent to the multi-break memory 15, and the VRAM by the CPU 1 is
The output of the address register 14 is selected as the VRAM address, and the write data from the CPU 1 is tRQ'd into the VRAM 4 via the buffers 16 and 17.

There is a line command in the drawing process, and this line command is used to move the start coordinates (DXo, DYo) of the straight line you are about to draw, the horizontal direction (in the X coordinate direction) of that straight line, and the vertical movement in the Y coordinate direction (φJ3). direction) mobile device! Draw a straight line] It is a cloak. In order to execute a line command, it is necessary not only to calculate the coordinates of a straight line, but also to perform logical operations with the color code data of the currently displayed screen.

FIG. 3 is an 11th diagram explaining the execution of a line command. This figure 3 shows 1 display screen, [”[, star 1~
Consider an example of the operation of a write command that draws a straight line from the coordinates (DXo, DYo).

First, CI) U 1 is star 1-coordinates (DXO,,
DYo), the object 1jll address with v r < ΔM4 is extracted, and the address is stored in the VRAM address 1 in the display control circuit 3.
: Set in response register 14. Cl) tJ 1 outputs lead] cloak, star 1 ~ coordinates (1) X
O.

The color code data in the VRAM 4 corresponding to DYo) is read. CPUIG, perform a logical operation between the node data and a certain color code data to create a color code data for a straight line.

Color-J-1; data related to this created straight line can be changed from star 1 to PI! by the write command. ! Mark (
■1 corresponding to DXo, DYo> is written into ΔM4.

Next, the CPU 1 calculates the coordinates (0) and calculates the coordinates (DXl, DY) of the second dot constituting the straight line to be drawn.
1) through a sieve. Then, the linear color code data is written into the V RAM 4 by a similar operation. Furthermore, the third dora]・'s seat all(1)X2. D.Y.
2) By sequentially repeating the above operations NX times, a straight line can be drawn on the screen.

Recent personal computer displays have been developed in response to requests to reduce the size of the computer and reduce the amount of time required to use the computer. B1 is designed to reduce the amount, for example, the number of gates and the number of ICJR children, and the burden on the 1J software uni j' increases accordingly.

[Problems with the background technology] As shown in the conventional line command execution example above,
The processing is all burdened by c Pv i, and the color code data Nori 1 Dri/Ri 1 ~, coordinates! ! 1n, it takes a very long time to generate a physical address, so there is a problem that the processing efficiency of line commands is low.

[1.1 of the invention] The present invention has been made in order to solve the problems of the conventional art mentioned in 1.
Therefore, the object of the present invention is to provide an O1I display system for a computer which can reduce display operation time (by one hour) regarding line commands.

[Summary of the Invention] In order to achieve the above object, the present invention comprises a line command execution means using hardware.

[Embodiment of the Invention] FIG. 4 shows an embodiment of the present invention.

A display timing clock [one clock generation] A one clock generator 31 is provided, and according to the display timing clock, a digit counter, a line counter, etc. are used to generate the OR1 screen display timing JJ and VRAM address.
A counter 32 is provided which shifts the j counter to the right.

A data bus 41 from CPtJl is connected to a register data bus 43 via a buffer 42. CPU
A register pointer 44 holds the number of the register in the display control circuit 3 that is accessed by 1, and a register selector decoder 45 decodes the output of this register pointer/14 to designate each register. In addition to the register I function, this register pointer 44 also has the register I function.
-Has an up function. When each register is completed, the count increases by one. Therefore, it is possible to automatically specify registers one after another.

Further, the TI mantle register 46 holds command information from the CPU 1, and the video Cl) U 47 performs processing related to display data in accordance with the commands from the CPU 1. The SR register 48 holds the status of this VIF; A-CPU 47 to CI) Ul.

Furthermore, the video CPU 47 has an internal calculation register ΔCC and can perform necessary calculation processing according to commands.
When accessing the VRAM4, the VRAM address register/counter 37 holds the VRAM address.
Ru. The color code register 33 holds write data to V+<ΔM4 and read data from VRAM4.

The constituent elements described above are the features of the present invention.

In addition, there is a DX register/counter 58 that holds the number on the horizontal
register/counter 59 and DX.

A DXY address synthesis circuit 57 is provided which creates a physical address of the VRAM 4 according to each output of the DY address/counters 58 and 59.

Above DX, DY register/counter 38.39°58.
In addition to the register function, 59 also functions as an up/down counter.

Furthermore, display 1. The VRAM address bus 36 in the II control circuit 3 is connected to the address line 56 of the VRAM 4 via a buffer 55. V in display control circuit 3
The RAM data bus 35 is connected to the VR via the buffer 53.
It is connected to AM data line 54.

The NX register 61 holds the amount of movement in the horizontal direction (X coordinate direction) from the start coordinate of the straight line, and the NY register 6
3 holds the amount of movement in the vertical direction (Y coordinate direction) from the start coordinates (DXo, DYo> of the straight line indicated by "-").The horizontal direction X flag 60 indicates the positive direction when it is rOJ. (rightward), and indicates a negative direction (leftward) when it is "1" 1. The vertical 1-erection Y flag 62 indicates a positive direction (downward) when it is "0"; “1” indicates negative direction (upward direction).△
The LU (arithmetic unit 1 to) 51 outputs the output of the color code register 33 and D according to the control from the video CPU 47.
Logical operations with the output of register 52, e.g. IMF, A
ND, OR1] Performs OR, NOT calculations.

The following are the characteristic components of the present invention, shown at $11
In addition to these components, b components exist in the 111 circuit 3. However, the explanation of components that are not particularly necessary in 1 for explaining the operation of the present invention will be omitted.

Next, the operation of the embodiment described in section 2 will be explained.

CP jJ 1 needs to store the information necessary to execute the line command in each register of the display ll1l111 circuit 3 in advance. When the CPU 1 accesses each register shown in FIGS. 5 and 6, the register number of the register to be accessed is stored in the register pointer 44.
hit, then read/write 1~.

The CPU i sets the start coordinates (DXo, DYo) of the straight line to be drawn in the X register/counter 58 and the DY register/counter 59. The DX register/counter 58 is a DXL as shown in FIG.
Same as (register #36) [)
), and the DY register/counter 59 is
It consists of L (register #38) and DYH (register #39).

In addition, the horizontal direction (x coordinate direction) from the start coordinates <DXo, DYo) is transferred to the NX register 6.
1, and the movement ff1NY in the weight l'j direction (Y coordinate direction) is written to the NY register 63.

Figure 3 shows 1J: Uni, the above straight line is the starting coordinate (DX
Since both the X and Y directions are in the positive direction when viewed from DYo), the direction 3-in X7 lag 60 and the direction Y flag 62 are set to [01]. The direction X flag 60 corresponds to bit 2 of the argument register (register #46), and the direction Y flag 62 corresponds to bit 3 of the argument register (register #46). Then, the specific data used to perform the screen color-1-code calculation and create straight 7J-color data is stored in the 7J-color register 33. “This color” - Dresister 33
corresponds to CI-R register #44) shown in FIG.

The CPU 1 executes rol 11 according to the command-1-code table in FIG. 7 and the logical A verification load table in FIG.
Create a command code of 00111J and certify it to the command register 46 (register #45). This-”
-1'0111J indicates a line command, and the lower 4 pins +-roo
ii'' is a 1] logical A veriation code, indicating that it is an exclusive OR.

5 shows the contents of registers #32-42, and FIG. 6 shows the contents of registers #43-46 and register #2. In response to the content of #8, this is b.

FIG. 7 is a diagram showing the =1 cloak] - code.

In this figure, fVDcJG, t, & 1jl t
ill l'jl 'tH3 is 1J.

Video CI) When the U 47 receives the command code J3 and the logical Averation code from the CPU 1, the U 47 executes SI' (command executable bit 7 of the register 48 (register shown in FIG. 6). #2
rcEJ ) to start execution and processing of that command.

Next, the bidet ACPU 47 reads the color code from the VRAM 4 created by the DXY address synthesis circuit 57 from the DXX register/counter 58l) and the Y register/counter 59 that hold linear coordinates, and reads the color code from the D register Set to 52.

The data in the register 33 set by the CPU 1 and the data in the register 52 read from the linear drawing area are as follows:
The ALU (logical operation-1 nits 1~) 51 executes a logical operation (Jl*(l! logical sum). As a result, color-1 code data for straight line drawing is created.

The newly calculated and created color code data is V.
VRA via RAM data bus 35 and buffer 53
It is output onto the M data line 54 and written into the VRAM 4 in accordance with the physical address of the area where a straight line is to be drawn, which is created by the DXY address synthesis circuit 57.

By completing the above operations, the drawing of one dot along the above straight line is completed.

The bidet 71 CPU 47 inputs the coordinates indicated by the contents of the DX register/counter 58 and DY register/counter 59, and the NX register 61 and NY register 63.
The coordinates 81 are based on the amount of movement/direction indicated by the contents of
Calculate the I of the second dot J5 [) on the above straight line! Calculate P (DXl, DYI). At the same time, Lkizagura! l According to the standard, NX counter 64 and N
Y Kakarata 65 is the movement m to the second dora 1- (pukaran 1-up).

Note that the NX counter 64 and NY counter 65 are cleared by the via' ACP IJ 47 at the start of the line command.

The coordinates (DXl, 1) Yl) of the second driver 1~ are again stored in the DX register/counter 58 and the DY register/counter 59, and by the same procedure as above, the coordinates (DXl, 1) Yl) of the 2Mth driver 1~ Drawing is executed.

bidet;t CI) U 47 is the NX register 61
The X counter 64 matches, and the NY register 63 matches the N
When a match with the Y character data 65 is detected, it is determined that the line command has been completed, and the command execution-1 ing < C[) bit of the SR register 48 is cleared to notify the CPU 1 of the end of the command.

Next, the straight line algorithm described above will be explained in detail.

First, let (NY) be the value of the NY register, and (NX) be the value of the NY register.
Let the value of the X register be (NY) > (NX > (). The calculation register in the video Ac p u is called △OC, and its value is expressed as (△CC). The flowchart in Fig. 9 shows 1) By moving the NX J counter, DX counter, NY J counter, and DY counter one by one, XY traces the physical address of the core wire.

DX counter, DY Kakarata count is DIRX, D
IRY's 1st shift determines the direction of the countdown from 1st to 1st and 1st to IJ1.1.

Next, if (NY) <(NX>
This is done by swapping NX5DX and DY. As a result, a straight line is raced with the X-axis direction as the main axis.

-Here, 1-51! By this principle, the CPU can perform the core wire drawing process without any burden by simply outputting line commands. Therefore, the time required for the drawing process becomes extremely short.

[Effects of the Invention] As mentioned above, Kikomei can immediately handle most of the software processing time related to line commands in display operations using hardware, which improves the processing efficiency related to line commands. It has the effect of increasing the speed of display memory access.

Further, in this case, there is an effect that the necessary increase in hardware is relatively small.

[Brief explanation of drawings]

Figure 1 shows a conventional general display device, and Figure 2 shows a lit! J3LJ display in Figure 1 1. II. A block diagram showing the 111 circuit, Fig. 3 is an explanatory diagram of line commands, Fig. 4 is a diagram showing one embodiment of the present invention, and Figs. 5 and 6 are based on the above embodiment. (Figure 7 shows the contents of each register, Figure 7 shows the cloak code, Figure 8 shows the 1) logical A veriation, and Figure 9 shows the flowchart of the j' algorithm of the line command real 1j. There are 1-r Chars. 1...CPU, 2...Main memory, 3...Display control circuit, 4...VRAM (video memory), 33...
・Color=1-dore register, 35...VRAM address bus, 47...video CPU, 51...△LU(
Logical operation] nit), 52...D register, 57...
・DXY address synthesis circuit, 58...I) X register/counter, 59...DY register/counter, 6
1...NX register, 63...NY register. Figure 1 Figure 2 1, 3 Figure 5 #33 Huge [42 lower] Construction [Ward [Ward M] 5XH (V-
sXHigh) $34 [Tomi] =]
[)〼1] 〒i2PSYL(゛North Y Low) Well 35 Big =] Possible] "Koshimo Higashiga■mouth 5Y)l (Source Y High1637 fj[I]q■Ding b King DX
)l [%X7J->IIin
f<X%#-Shikon Y Low $39 [To E-5]
Votes ==== Nico? = Gopi■Ma1=Maishi] oy+(U9guruta-si, shiY Highlf$41 o o o
o o ONX9NX NXH(1'JeL
ghl$42 Qko IY NY NY2NYIN MaQ
NYL ()”J
Color register) #45 E* * *, R”￥4
ARGR (y-F,,+>bb cis9) #46 [day

[
φ day Roku] different condolence F layer i eye Σ]! [Call 1 cMR (Command Cashier) #2 [I Wa I “Bottom” = Ipego Ward []
Two===? ] SR (Status System) 7th. Figure 8

Claims (4)

[Claims] (1) In a storage device that logically constitutes a display plane, means for specifying the start coordinates of a straight line; means for maintaining movement in the horizontal direction from the start coordinates; and movement m in the vertical direction from the start coordinates. and a means for holding: A display 1 characterized in that it is possible to draw a straight line with a predetermined length in a predetermined direction from the starting coordinates.
．． II lit device. (2) In a storage device that logically constitutes a display plane, means for specifying the start coordinates of a straight line; means for retaining the amount of movement in the horizontal direction from the start coordinates; and the amount of movement in the vertical direction from the start coordinates. means for holding; and logical calculation means for performing rAl'c logical calculations on two predetermined color code data; and: capable of drawing a straight line from the starting coordinates in a predetermined direction and with a predetermined length. A display control device characterized by: (3) The display control device according to claim 1, wherein the storage device is a display memory. (4) The display control 11' according to claim 1, wherein the start coordinates are indicated by values on the X and Y coordinates.