JP2001092984A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a texture memory address at high speed without requiring a computing element even when the lateral width of texture source data is arbitrary in texture mapping. SOLUTION: The texture source data are separated for each of data of the same (v) coordinate, aligned to the left and written in a texture memory 4 by a data aligning part 3, and a texture memory address generating part 6 newly regards the closest value of the power of '2' greater than the lateral width of the texture source data as the lateral width of the texture source data and generates the texture memory address from a texture coordinate (u, v) in a combination circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for drawing texture mapping and patterns in the field of computer graphics.

[0002]

2. Description of the Related Art In recent years, drawing processing using texture mapping is often performed in the field of computer graphics. The texture mapping is to paste a pattern separately defined as texture source data on a polygon. FIG. 16 shows an example of texture mapping, in which polygons (P0, P1, P2,
P3), the texture (T0, T1, T2, T
3) corresponds to this.

[0003] Texture mapping is realized by reflecting pixel values of texture coordinates (u, v) on polygon coordinates (x, y). That is, the correspondence between the polygon coordinates (x, y) and the texture coordinates (u, v) is calculated. Regarding the calculation method, as shown in JP-A-8-161510 and JP-A-9-73547, a primary conversion,
There are secondary transformation and inverse mapping.

[0004] Texture source data is stored in a memory, and a memory address is calculated from texture coordinates (u, v) to retrieve corresponding data. The width of the texture source data is TDX, the number of bits per pixel is P,
Assuming that the number of bits per word of the memory is D, the formula for calculating the memory address is as follows.

Memory address = (TDX × v + u) × P
/ D where (u, v) = (2,1), TD
Taking X = 7, P = 8 and D = 32 as an example, the memory address = (7 × 1 + 2) × 8/32, and the quotient is 2 and the remainder is 1.

FIG. 17 shows the assignment of texture coordinates (u, v) to the texture memory in this case. In the drawing, (0, 0), (0, 1),... Mean pixel data assigned by (u, v).

As shown in FIG. 17, a quotient 2 means a memory address, and a remainder 1 means a pixel position in a word indicated by the memory address.

[0008]

In order to calculate the memory address by hardware, an arithmetic unit such as a multiplier is required, so that the circuit scale is increased.

If the TDX is limited to a power of two, a memory address can be obtained only by combining u and v bit strings as shown in FIG. FIG.
8, each of u and v has a data width of 8 bits, and the number of bits per pixel is 8 bits.
The number of bits per word is 32 bits, and the number of words in the memory is 256 words. In the figure, u [0], u [1],
.., V [0], v [1],... Mean the 0th bit, 1st bit,.

According to this method, since it can be realized only by a combinational circuit, the circuit scale is small and a memory address can be generated at high speed. However, in this case, there is a disadvantage that TDX cannot be set arbitrarily. An object of the present invention is to provide a device that can arbitrarily set TDX and generate a memory address at high speed when a memory address is generated from texture coordinates (u, v).

[0011]

In order to achieve the above object, according to the first aspect of the present invention, a texture memory for storing texture data for performing texture mapping and a texture source data having the same v coordinate are used. A data alignment unit that separates the data for each data and writes them to the texture memory in a left-justified manner, a texture memory address generation unit that generates a memory address of the texture memory from texture coordinates (u, v), and a texture coordinate (u , V), and an image memory interface for writing the texture data corresponding to the polygon coordinates (x, y) of the image memory to be displayed on the screen.

The invention according to claim 2 of the present invention provides:
2. The texture memory address generation unit according to claim 1, wherein a memory address is generated by regarding a value of a power of 2 closest to and larger than the width TDX of the texture source data as a new width of the texture source data. is there.

Further, the invention according to claim 3 of the present invention provides:
The texture memory address generator according to claim 2, wherein the width TDX of the texture source data is smaller than the number of pixels that can be stored in one word of the texture memory according to claim 1, and the number of pixels that can be stored in one word in the texture memory. A memory address is generated by regarding the same value as a new width of the texture source data.

The invention according to claim 4 of the present invention provides:
A data processing unit is provided between the data alignment unit according to claim 1 and the texture memory, the data processing unit performing deformation in units of data having the same v coordinate.

The invention according to claim 5 of the present invention provides:
2. The image memory interface according to claim 1, wherein if the texture data corresponding to the texture coordinates (u, v) is 0, the color data is 0; (X, y).

The invention according to claim 6 of the present invention provides:
The data processing unit according to claim 4 performs two processes in the order of horizontal processing and vertical processing. In the horizontal processing, if the enlargement / reduction mode W is the same size, the data is output from the data alignment unit. If the data is sent to the next mode as it is, and if the enlargement / reduction mode W is half-width, the data output from the data alignment unit is ORed with the even-numbered bit and the next bit, and then sent to the next step. If the reduction mode W is double-width, the data output from the data alignment unit is
Each bit is expanded to 2 bits and sent next. In the vertical processing, if the enlargement / reduction mode H is the same size, the data sent from the horizontal processing is output as it is, and the enlargement / reduction mode H If it is a half-width, the data sent from the lateral processing is ORed with the data sequence of even-numbered coordinates and the next data sequence, and output.
Is a double-width, the data sent from the horizontal processing is output such that a data string for each v coordinate is written twice to the texture memory.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 of the present invention will be described below in detail.

First, the data width per pixel in this embodiment is defined as 8 bits.

FIG. 1 is a block diagram showing the configuration of an image processing apparatus according to the present invention. In FIG. 1, 1 is a source data storage memory, 2 is a data buffer, 3 is a data alignment unit, 4 is a texture memory, 5 is a texture memory access control unit, 6 is a texture memory address generation unit,
7 is a selector, 8 is an image memory interface, and 9 is an image memory.

In the figure, the numbers 0 and 1 are described on the input side of the selector, which means that the input line is selected according to the value of the memory access mode which is a signal for switching the selector. .

The source data storage memory 1 is a memory for storing texture source data. The memory 1 for storing source data stores 32-bit data in word units. Data buffer 2
Has a role of temporarily storing the texture source data extracted from the source data storage memory 1 and sending the texture source data to the data alignment unit 3. When the data of different v-coordinates are mixed in the texture source data sent from the data buffer 2, the data aligning unit 3 separates the data of the same v-coordinate and aligns the data to the left and outputs it. The texture memory 4 is a memory in which the number of bits per word is 32 bits and the number of words is 256 words.
From here, texture data is extracted.

The texture memory 4 writes and reads data to and from the address indicated by the texture memory address output from the selector 7. The texture memory access control unit 5 controls writing and reading of data to and from the texture memory 4 in the texture mapping process.

First, when the texture data is stored in the texture memory 4, the texture memory 4 is set to the writing state, and the memory access mode for controlling the selector 7 is set to 0. Then, the address A is sequentially incremented from 0 so that the data output from the data alignment unit 3 is sequentially written from address 0 of the texture memory 4 and output.

Next, when the texture data is taken out from the texture memory 4 and pasted on a polygon, the texture memory 4 is set to the read state and the memory access mode is set to 1. Then, the closest power-of-two value equal to or greater than TDXa, which is the width of the texture source data, is expressed as TD
Xb is sent to the texture memory address generator 6.

It should be noted that TDXa is stored in the texture memory 4
TDX if less than the number of pixels that can be stored in a word
b is set to the same value as the number of pixels that the texture memory 4 can store in one word. For example, when TDXa = 1, the number of pixels that the texture memory 4 can store in one word is 4, so that TDXb = 4.

The texture memory address generation unit 6 calculates T
Assuming that DXb is the horizontal width of the texture source data, an address B is generated from the texture coordinates (u, v) by a combinational circuit when TDX is limited to a power of 2 as shown in FIG. The selector 7 selects the address A if the memory access mode is 0, and selects the address B if the memory access mode is 1 and outputs it as a texture memory address for the texture memory 4. The image memory interface 8 determines the pixel position from the u coordinate of the texture data output from the texture memory 4 as shown in the item of the pixel position in the word indicated by the memory address in FIG. The texture data is extracted, and the extracted texture data is written to the polygon coordinates (x, y) of the image memory 9. The image memory 9 is a memory for storing each pixel data of a polygon. When displaying the drawn figure on a display or the like, the image memory 9
Target data stored in.

Here, a description will be given of a series of flow of processing for performing texture mapping when TDXa = 7.

First, texture source data is sequentially taken out from the source data storage memory 1, passed through the data buffer 2, and aligned by the data alignment unit 3, and stored in the texture memory 4. Since the texture memory access control unit 5 sets the memory access mode to 0, the address A is selected as the texture memory address.

FIG. 2 shows the state of the texture data stored in the texture memory 4 from the source data storage memory 1 via the data buffer 2 and the data alignment unit 3.

FIG. 2A shows a memory 1 for storing source data.
Shows the state of assignment of the texture coordinates (u, v) for the data stored in. In the figure,
(0, 0), (0, 1),... Mean the pixel data assigned by (u, v) as in FIG. FIG. 2B shows the assignment state of the texture coordinates (u, v) for the data stored in the texture memory 4. In the drawing, X indicates that any data may be used. That is,
The data arranging unit 3 puts appropriate data in the X part. From FIG. 2B, it can be seen that the texture data is stored in the texture memory 4 in the same state as in the case of TDX = 8. After the necessary texture data is stored in the texture memory 4, the polygon coordinates (x,
For y), the process proceeds to a process of pasting the texture data of the corresponding texture coordinates (u, v). Since the texture memory access control 5 sets the memory access mode to 1, the address B is selected as the texture memory address.

The closest power-of-two value of 8 with TDXa = 7 or more is set as TDXb. The texture memory address generation unit 6 regards TDXb = 8 as the width of the texture source data, and
An address B is generated as shown when X is eight.

For example, when (u, v) = (2, 1), as shown in FIG. 3, the address B is 2, and the pixel position in the word indicated by the memory address is 2. (U, v)
FIG. 4 shows how texture data stored in the texture memory 4 is extracted when = (2, 1).

The texture data thus extracted is written to the polygon coordinates (x, y) of the image memory 9 via the image memory interface 8.

As described above, even when TDX is not a power of 2, memory addresses can be generated in the same manner as when TDX is limited to a power of 2, so that the circuit scale is smaller than that using an arithmetic unit. A small and fast memory address can be generated.

Hereinafter, the second embodiment of the present invention will be described in detail.

FIG. 5 is a block diagram showing another configuration of the image processing apparatus according to the present invention. In this image processing device,
Pattern data having a data width of 1 bit per pixel is handled as texture data. Such pattern data is often used for character drawing. Since the data stored in the texture memory 4 has a data width of 1 bit per pixel, the texture memory address generation unit 6 uses the texture coordinate (Tx) in the combinational circuit when TDX is limited to a power of 2 as shown in FIG. The address B is generated from u, v). A data processing unit 10 is provided between the data alignment unit 3 and the texture memory 4 and has a role of processing pattern data in the enlargement / reduction mode W and the enlargement / reduction mode H. The data processing unit 10 performs two processes in the order of the horizontal processing and the vertical processing on the data separated by the data alignment unit 3 for each data of the same v coordinate and aligned left-justified. The enlargement / reduction mode W and the enlargement / reduction mode H input to the data processing unit 10 include three modes, ie, the same size, half size and double size.

First, the lateral processing will be described. If the enlargement / reduction mode W is the same magnification, the data output from the data alignment unit 3 is sent next as it is. If the enlargement / reduction mode W is half-width, the data output from the data alignment unit 3 is logically ORed with the even-numbered bit and the next bit, and then sent. If the enlargement / reduction mode W is a double-width mode, each bit of the data output from the data alignment unit 3 is expanded to 2 bits, and then transmitted.

Next, the vertical processing will be described. If the enlargement / reduction mode H is the same magnification, the data sent from the horizontal processing is output as it is. If the enlargement / reduction mode H is a half-width, the data sent from the horizontal processing is ORed with the data sequence of even-numbered coordinates and the next data sequence and output. If the enlargement / reduction mode H is a double angle, the data sent from the horizontal processing is output such that a data string for each v coordinate is written twice to the texture memory 4 twice. The image memory interface 11 sets the pattern data fetched from the texture memory 4 to 0.
If the pattern data is 1, the color data 0 is stored, and if the pattern data is 1, the color data 1 is stored in the polygon coordinates (x, y) of the image memory 9.
Write to. The color data 0 and 1 each have a data width of 8 bits per pixel.

Here, how the data processing unit 10 enlarges / reduces the size and size of the character “matsu” of 16 × 16 as shown in FIG. 7 as an example of the texture source data will be described.

FIG. 8 is a diagram showing a modification process of the data in which the v coordinate of the texture source data is 0 when the enlargement / reduction mode W is half-width and the enlargement / reduction mode H is the same size. Logical OR with bit.
When the above process is performed on all data, the result is as shown in FIG.

FIG. 10 is a diagram showing a process of transforming the data in which the v coordinate of the texture source data is 0 or 1 when the enlargement / reduction mode W is the same magnification and the enlargement / reduction mode H is a half-width. The logical sum of the data string and the next data string is calculated. When the above processing is performed on all data, the result is as shown in FIG.

FIG. 12 is a diagram showing a process of transforming data in which the v coordinate of the texture source data is 0 when the enlargement / reduction mode W is the same magnification and the enlargement / reduction mode H is the double angle.
The data is extended to two columns. When the above processing is applied to all data, the result is as shown in FIG.

FIG. 14 is a diagram showing a process of deforming the data in which the v coordinate of the texture source data is 0 when the enlargement / reduction mode W is a double angle and the enlargement / reduction mode H is the same magnification.
Each bit is extended to two bits. When the above processing is applied to all data, the result is as shown in FIG.

The hatched pixels in FIGS. 7 and 8 correspond to 1 of the pattern data.
Pixels not hatched correspond to 0 in the pattern data.

[0045]

According to the present invention, even when an arbitrary TDX is handled, the memory address can be generated in the same manner as in the case where the TDX is limited to a power of 2, so that the circuit scale is smaller than that using an arithmetic unit. A small and fast memory address can be generated. Further, even when data having different v-coordinates are mixed in the same word of the texture source data, the data is separated for each data of the same v-coordinate, so that deformation processing such as enlargement / reduction of the texture data is performed at high speed and easily by hardware. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a state of texture data stored in a texture memory 4 from a source data storage memory 1 via a data buffer 2 and a data alignment unit 3;
FIG. 3A shows the state of assignment of texture coordinates (u, v) for data stored in the source data storage memory 1. FIG. 4B shows the texture coordinates (u) of data stored in the texture memory 4. , V)

FIG. 3 is a diagram showing a memory address when (u, v) = (2, 1) and a pixel position in a word indicated by the memory address;

FIG. 4 is a diagram showing how texture data stored in a texture memory 4 is extracted when (u, v) = (2, 1).

FIG. 5 is a block diagram showing a configuration of another image processing apparatus according to the embodiment of the present invention.

FIG. 6 is a diagram showing memory address generation when texture data has a data width of 1 bit per pixel and TDX is limited to a power of 2;

FIG. 7 shows that the texture source data has a length × width = 16 × 1.
Figure 6 shows that it is the character "matsu"

FIG. 8 is a diagram showing a process of transforming data in which the v coordinate of the texture source data in FIG.

FIG. 9 is a diagram in which all the texture source data in FIG. 7 are transformed when the enlargement / reduction mode W is half-width and the enlargement / reduction mode H is the same magnification.

FIG. 10 is an enlargement / reduction mode W in the same magnification and an enlargement / reduction mode H
FIG. 7 is a diagram showing a modification process of data in which the v coordinate of the texture source data in FIG.

FIG. 11 shows an enlargement / reduction mode W at the same magnification and an enlargement / reduction mode H
Is a half-width case where the texture source data of FIG. 7 is all transformed.

FIG. 12 shows an enlargement / reduction mode W in the same magnification and an enlargement / reduction mode H
FIG. 7 is a diagram showing a deformation process of data in which the v coordinate of the texture source data in FIG.

FIG. 13 shows an enlargement / reduction mode W in the same magnification and an enlargement / reduction mode H
Is a double-width image, all of the texture source data in FIG. 7 are transformed.

FIG. 14 is an enlargement / reduction mode W in a double angle mode and an enlargement / reduction mode H
FIG. 7 is a diagram showing a modification process of data in which the v coordinate of the texture source data in FIG.

FIG. 15 shows the enlargement / reduction mode W in double-angle mode and the enlargement / reduction mode H
Fig. 7 is a diagram in which all the texture source data in FIG.

FIG. 16 is a diagram showing an example of texture mapping.

FIG. 17 is a diagram showing an assignment state of texture coordinates (u, v) to a texture memory;

FIG. 18 is a diagram showing memory address generation when texture data has a data width of 8 bits per pixel and TDX is limited to a power of 2;

[Explanation of symbols]

 Reference Signs List 1 memory for storing source data 2 data buffer 3 data alignment unit 4 texture memory 5 texture memory access control unit 6 texture memory address generation unit 7 selector 8, 11 image memory interface 9 image memory 10 data processing unit

 ────────────────────────────────────────────────── ─── Continued on the front page F term (reference) 5B047 AA03 EB12 EB14 5B057 CA01 CA08 CA13 CA17 CB01 CB08 CB13 CB16 CC04 CF10 CH01 5B080 AA13 CA09 DA03 GA22

Claims (6)

[Claims] 1. A texture memory for storing texture data for performing texture mapping, a data alignment unit for separating texture source data for each data of the same v coordinate, aligning them left-justified, and writing the data to the texture memory; A texture memory address generation unit for generating a memory address of the texture memory from the texture coordinates (u, v); and a polygon coordinate (x, x) of an image memory to be displayed on the screen, the texture data corresponding to the texture coordinates (u, v). An image processing apparatus, comprising: an image memory interface for writing in y). 2. The texture memory address generating unit generates a memory address by regarding a value of a power of 2 closest to and greater than the horizontal width TDX of the texture source data as a new horizontal width of the texture source data. Item 2. The image processing apparatus according to Item 1. 3. The texture memory address generator, when the width TDX of the texture source data is smaller than the number of pixels that can be stored in one word of the texture memory, the same value as the number of pixels that the texture memory can store in one word. 3. The image processing apparatus according to claim 2, wherein the memory address is generated by newly considering the width of the texture source data. 4. The data processing unit according to claim 1, further comprising a data processing unit for performing a deformation in units of data having the same v coordinate between the data alignment unit and the texture memory. Image processing device. 5. The image memory interface according to claim 1, wherein the texture data corresponding to the texture coordinates (u, v) is 0, the color data is 0, and if the texture data is 1, the color data is 1. 5. The image processing apparatus according to claim 1, wherein the coordinates are written at coordinates (x, y). 6. The data processing unit performs two processes in the order of horizontal processing and vertical processing. In the horizontal processing, if the enlargement / reduction mode W is the same size, the data processing unit outputs the data. If the scaling mode W is half-width, the data output from the data alignment unit is ORed with the even-numbered bit and the next bit, and then sent, If the enlargement / reduction mode W is a double-width mode, each bit is expanded to 2 bits for the data output from the data alignment unit, and then transmitted,
In the vertical processing, if the enlargement / reduction mode H is the same magnification, the data sent from the horizontal processing is output as it is. If the enlargement / reduction mode H is half-width, the data sent from the horizontal processing is output. And v is the logical sum of the data sequence of even-numbered coordinates and the next data sequence, and outputs the result. If the enlargement / reduction mode H is a double angle, the data sent from the horizontal processing is 6. The image processing apparatus according to claim 5, wherein a data string for each v coordinate is output so as to be written twice to the texture memory.