JP3278853B2 - Graphic drawing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic drawing apparatus for displaying figures, characters, and the like on a display device such as a display, and more particularly to a graphic drawing apparatus operated at the same time by operating a plurality of processors simultaneously.

[0002]

2. Description of the Related Art The so-called graphics processing for displaying graphics and characters on a display has become popular with the spread of personal computers and word processors, and has been recognized as an important element of a man-machine interface with a user. Therefore, higher functionality and higher performance are being promoted. The basic functions of the graphics processing are straight line drawing and character drawing. Processor LSIs capable of processing these at high speed are supplied by many manufacturers.

The processing method in a conventional processor is as follows. First, the straight line drawing is a process for each pixel, generates a coordinate point on a straight line, calculates an actual address of a memory corresponding to the coordinate point, reads data from the memory corresponding to this address, and writes the data into a line. The basic processing is to perform a logical operation or an arithmetic operation on seed data (designation of a solid line, a chain line, a dashed line, etc.) and write back to the original address.

[0004] A method called digital differential analysis (hereinafter referred to as DDA) for generating coordinates of a point on a straight line is well known, and is employed in almost all processors. This DDA will be described briefly. The XY coordinate plane to be used when generating a straight line is a plane in which each pixel of the memory corresponds to a discrete XY grid point. By writing data on the grid point closest to the new straight line, the straight line is obtained. Realize drawing.

A method for accurately and easily obtaining the approximate lattice point is a digital differential analysis method. According to this method, when the coordinates on a certain straight line are obtained, the coordinates of the next point can be obtained in consideration of the error from the true straight line. Never leave a true straight line.

On the other hand, character drawing is realized by a rectangular area transfer function. A character is generally defined by data of n × n pixels, and a character portion is prepared as “1” and a background portion is set as “0” in the rectangular area for each character. This data is called a "character font" and is generally provided by a manufacturer as a ROM storing several thousand characters. This ROM is used to display characters on the display.
, And a desired character font is read from the memory and written in a predetermined position on the memory. For example, 640
To display a 24 × 24 dot character in the upper left corner of a × 400 display, write the first 24 bits of the character font into the first 24 bits of the first line of memory and write the next 24 bits of the character font. The operation of writing to the first 24 bits of the second line of the memory may be performed for 24 lines. This processing is called rectangular area transfer.

[0007]

As described above, the straight line drawing function and the rectangular area transfer function are implemented as LSIs, but their performance is still insufficient as a man-machine interface. This is generally due to the memory access time causing a performance bottleneck. Since a DRAM is generally used as a display memory, its cycle time is about 200 ns.

For a straight line, data to be written is generally read first, and a logical operation or an arithmetic operation is performed between this data and the line type data to be written.
Times memory access. In applications such as CAD and document creation applications, it is common to draw 100,000 lines per screen (average length per line = 10 dots). It is common to redraw all of these straight lines. Therefore, (200 ns + 200 ns) ×
10 dots x 100000 lines = 400 ms.

As for characters, in order to transfer 24.times.24 dots of characters with a data width of 16 bits to 1000 characters, reading of character data, data reading of a transfer destination,
Since three memory accesses of data write to the transfer destination are used as a unit, (200 ns + 200 ns + 200 n
s) × 2 times / line × 24 lines × 1000 characters, which takes about 30 ms. This is the case for black and white, but 2
When it comes to 56 colors, it is 8 times more, ie 240m
It also takes s. The 1000 characters is a general number of characters displayed on the screen, and when scrolling this screen, only four times can be performed per second, which is very slow. Character drawing can be accelerated to some extent by increasing the bus width of the memory. For example, assuming a 32-bit width in the above example, the performance simply doubles.

As described above, in the prior art, the straight line has reached the access bottleneck of the memory, and there has been no method of increasing the speed of character drawing other than increasing the bus width of the memory.

An object of the present invention is to solve the above-mentioned problem and to provide a graphic drawing apparatus capable of processing both straight line drawing and rectangular area transfer at high speed.

[0012]

According to the present invention, there is provided a graphic drawing apparatus for drawing a graphic in a memory defined on XY information by simultaneously operating a plurality of processors, wherein each processor has at least a linear drawing function. And n × m processors operable to process each n × m pixel assigned to every n pixels in the X direction and every m pixels in the Y direction for the rectangular area transfer function, and n pixels in the X direction each, allocated to be accessed for each m pixels in the Y direction, and the n × m pieces of memory modules for storing pixel information respectively, wherein each processor and these processors Niso
A memory bus connecting each of the corresponding memory modules ; and a plurality of processor buses connecting all of the processors. one bus and selected by the selection signal when performing the selecting means and the line drawing function connected to said each processor of the data transfer between processors without, calculates the straight line drawing
As described above, when the selection signal is generated and the rectangular area transfer function is performed, the memory in which the transfer source data is stored is stored.
The destination data is stored from the processor connected to
Processor that is connected to the memory
Transfer destination data via the processor bus
Selection control means for dynamically changing the selection signal so as to perform a raster operation on the transfer destination data with the transfer source data is provided for each of the processors.

[0013]

The basic idea of the present invention is to provide n × m processors and operate them simultaneously, thereby increasing the performance up to n × m times at the same memory cycle time. That is, in the case of the straight line drawing, the n × m processors are operated by simultaneously processing a plurality of pixels by devising the generation of the DDA. In the case of the rectangular area transfer, the transfer data is transferred. By allocating an area to a plurality of processors and operating the plurality of processors simultaneously, data is transferred at a bus width of n × m times the bus width of one processor, thereby realizing a high transfer speed.

[0014]

FIG. 1 is a block diagram of a first embodiment of the present invention, and shows a figure drawing apparatus using a total of four (2 × 2) drawing engines. In the figure, 1-4 are drawing engines, 5
8 is a memory, 9 is a processor, 10 is a display processor, 11 is a display, 20 is a system bus, 21
24 to a memory bus, 25 to 30 a processor bus, and 31 to 34 a display bus.

FIG. 2 is a block diagram showing the internal structure of each of the drawing engines 1 to 4 shown in FIG. 1. 40 is a rectangular area transfer unit, 41 is a straight line drawing unit, 42 is a memory interface, 43 is a switcher, 50 Numerals 52 are internal buses.

First, in FIG. 1, parameters and commands related to drawing are transmitted to the host C via the system bus 20.
Input from a PU (not shown). The preprocessor 9 receives the command, interprets the command, and operates the drawing engines 1 to 4. Four drawing engines 1 to 1 that actually perform drawing processing in response to an instruction from the preprocessor 9
4 are connected to memories 5 to 8 via memory buses 21 to 24, respectively. Drawing on the memories 5 to 8 is performed via the buses 21 to 24. These drawing engines are interconnected via processor buses 25-30.

On the other hand, memories 5 to 8 are dual port
It comprises a display bus 31 for displaying on a display 11 and comprising a memory.
The display data is supplied to the display 11 by the control of.

Next, the configuration of the memories 5 to 8 will be described with reference to the configuration of FIG. This figure shows which memory corresponds to which pixel on a screen displayed on a display or the like, and the numbers in the figure show the numbers of the memories. The top left pixel of the screen is memory 5, the right pixel is memory 6,
The lower left corresponds to the data stored in the head address of the memory 7, and the right corresponds to the data stored in the head address of the memory 8. Since the screen is composed of the repetition of 2 × 2 pixels, the memories 5 to 8 hold pixel data at intervals of two pixels in the horizontal direction and the vertical direction, respectively.

Next, the operation of the four drawing engines 1 to 4 in the case of straight line drawing will be described. First, the preprocessor 9 calculates whether the drawing start position of the straight line and the inclination are 45 degrees or more or less. Since the parameters given by the CPU are the XY coordinates of the start point and the end point of the straight line, a drawing engine in charge of the pixel corresponding to the start point is obtained from these coordinates. Find out whether it is above or below. Thereby, the initial value of DDA of each drawing engine is determined.

The operation of each drawing engine will be described with reference to FIG. This figure is an example of a straight line in which the inclination between the straight line and the X axis is 45 degrees or less. The starting point coordinates are (2,2) and the slope is 2
/ 3 straight line. When the inclination is 1 or less, that is, 45 degrees or less as in this example, each rendering engine sets X from the initial value.
Is incremented by two, and when Y corresponding to X corresponds to the pixel in charge of itself, the memory is accessed to draw a straight line. If Y is not your pixel,
The processing for the pixel ends without any processing.

The initial coordinates are determined by the drawing engines 1 and 3 as (2,
2) The drawing engines 2 and 4 are (3, 2). Therefore, in the first drawing cycle, the pixel A is processed by the drawing engine 3 and the pixel B is processed by the drawing engine 4 at the same time, but the drawing engines 1 and 2 write back the read data as they are, so that they are not processed substantially. . This process is repeated only one half of the length of the straight line, and the number of repetitions is set in advance for each drawing engine.

Therefore, if the straight line length is an odd number, a certain drawing engine performs the above-described processing by "one half of the straight line length + 1" times and another drawing engine by "one half of the straight line length-1" times. Will be repeated. Subsequently, the pixels C and D are simultaneously processed by the drawing engines 1 and 4, respectively. In the next drawing cycle, the pixels E and F are simultaneously processed by the drawing engines 3 and 2.

Conversely, when the inclination with respect to the X axis is 45 degrees or more,
Each drawing engine increments Y by 2 and the Y
Is obtained, and rendering processing is performed only when the pixel is in charge of itself. By operating the four drawing engines at the same time, it is possible to realize twice the performance as compared with the case where only one drawing engine is operated. That is, when the inclination is 45 degrees or less, the number of rendering engines arranged in the X direction and the inclination are 4
In the case of 5 degrees or more, the number of drawing engines arranged in the Y direction is the number that can be operated simultaneously, and the drawing speed is improved in proportion to this number.

Next, the hardware operation will be described with reference to FIGS. In the case of straight line drawing, internally
Since the switcher 43 always connects the internal bus 52 and the internal bus 51, the straight line drawing unit 41 is always connected to the memory 5. That is, since each rendering engine processes only its assigned pixel, it does not access a memory connected to another rendering engine.

The drawing engines 1 to 4 have memories 5 to 5, respectively.
8 for generating an address for each memory, inputting data through the memory buses 21 to 24, and in each drawing engine, a memory interface 4
2. Operation is performed on the line type data in the straight line drawing unit via the internal bus 52, the switcher 43, and the internal bus 51, and the result is written to the memories 5 to 8 by the reverse route.

Next, the character drawing operation will be described. Since character drawing is realized by transferring a rectangular area, this function will be described.

The memory accessed by each drawing engine is:
The source area and the destination area. Each drawing engine reads the data of the transfer source area on the memory in charge of the drawing engine. At this moment, 2 × 2 pixels of data are stored in memory 5
That's the lead from 8. This data is sent to the drawing engine that is in charge of the transfer destination area. There are 16 combinations of the transfer source and transfer destination areas as shown in FIG.

That is, the numbers in the figure are the numbers of the memories, and when considering the upper left four pixels of the source area, there are four types of memory arrangements (1) to (4) depending on the pixel positions.
The transfer destination can have four types of memory arrangements (1) to (4) independently of the transfer source, so that there are a total of 16 combinations. One of the combinations can be selected in advance according to the leading coordinates of the transfer source and the transfer destination input from the CPU.
According to this selection, the switcher 4 of each drawing engine
3 connects the memory and the bus of the rectangular area transfer unit.

When performing rectangular area transfer, an operation called raster operation is performed between the source data and the destination data, and the operation result is written to the destination. Therefore, the processing procedure of each drawing engine is to generate an address for reading data from the transfer source, hold the transfer source data input via the switcher in the register in the rectangular area transfer unit, and then An address of the transfer destination area is generated to read the transfer destination data, a raster operation is performed between the transfer source data and the transfer destination data, and the calculation result data is written to the transfer destination. These processes operate in the same sequence on all drawing engines,
In addition, since the processor buses 25 to 28 are bidirectional, the internal buses 50 to 52 do not compete for a plurality of data transfers.

Next, referring to FIG. 6, a rectangular area transfer in the case where the start address of the transfer source is (2, 8), the start address of the transfer destination is (3, 3), and the size is 4 × 4 pixels. Will be described as an example. In this example, the start address of the transfer source area corresponds to the memory 7 connected to the drawing engine 3, and the start address of the transfer destination area corresponds to the memory 6 connected to the drawing engine 2. Therefore, the combination of the transfer source in FIG. 5 is (3) and the transfer destination is (2).

First, data A, B, C, and D in the transfer source area
Are output by the drawing engines 3, 4, 1 and 2, respectively, and the data is read. Of course, the addresses generated by the drawing engines 3 and 4 are different from the addresses generated by the drawing engines 1 and 2 by an address value for one line.

Transfer source data C read from memory 5
Are once input to the drawing engine 1 via the memory bus 21 , but are transferred to the processor bus 2 by the switcher 43 via the memory interface 42 and the internal bus 52.
9 is output. The data C is taken by the drawing engine 4, and the switcher 43 of the drawing engine 4
The bus 29 operates to connect the internal bus 50, and as a result, the data C is transferred to the rectangular area transfer unit 40 of the drawing engine 4.
Is taken in. Similarly, data D of the memory 6 is supplied to the drawing engine 3 via the processor bus 30, and data A of the memory 7 is supplied to the drawing engine 2 via the processor bus 30.
The data B of the memory 8 is input to the drawing engine 1 via the processor bus 29.

Next, the data read of the transfer destination area will be described. In this case, each drawing engine generates an address to be transferred to each of the memories 5 to 8 and reads transfer destination data. In this case, the transfer destination data is sent to the drawing engines 1 through
4 and the internal memory interface 4
2. Input to the rectangular area transfer unit 40 via the internal bus 52, the switcher 43, and the internal bus 50. Therefore, the input paths of the transfer source data and the transfer destination data are different, and the switcher 43 can change the bus connection relationship according to the phase.

When both the data of the transfer source and the data of the transfer destination are prepared, a raster operation between the two data is executed. In the case of the present embodiment, a logical operation and an arithmetic operation function are provided as raster operations in the rectangular area transfer unit. When both data are processed by a predetermined raster operation, the data is input to the memory interface 42 of each of the drawing engines 1 to 4 via the internal bus 50, the switcher 43, and the internal bus 52. Further, the four words of data are output to the memory buses 21 to 24 and written to the memories 5 to 8, respectively.

Thus, the data for four pixels has been processed. The four pixels E, F, G, and H on the right side of the transfer source continue to be processed.
Process. In this case, the relationship between the transfer source data and the transfer destination drawing engine is the same as the relationship described above. Further, when each drawing engine finishes processing for one line, the processing for the second line is started. The second line is substantially the processing of the third and fourth lines when viewed from the entire memory.
The size of the transfer area (the number of words in the X and Y directions)
Is not a multiple of 2, the rendering engine which does not need to perform processing at the time of processing the last word or line writes the transfer destination data as it is to the transfer destination, and substantially NO
P (No Operation).

FIG. 7 is a block diagram of a second embodiment of the present invention. In the present embodiment, the four processors of the first embodiment are regarded as one processor module, and the speed is further increased by using four processor modules.

In the figure, 61 to 64 are processor modules, 65 to 68 are memories, and 71 to 74 are memory modules.
Buses 75 to 80 are processor buses. This configuration is the same as that of FIG. 1 except that a preprocessor is incorporated in each processor module and each data bus is 32 bits (for 4 pixels). The internal configuration of the processor modules 61 to 64 is a portion surrounded by a dotted line in FIG. 1, and the memory buses 21 to 24 in FIG. 1 are put together to form a 32-bit bus, and the memory buses 71 to 64 in FIG. 74.

The operation of the graphic drawing apparatus thus constructed is almost the same as the case where the first embodiment uses 2 × 2 drawing engines, but considers 4 × 4. LS for one processor module 61 to 64
If it is I, a multiprocessor system can be easily constructed.

Although 2 × 2 processors are used in the first embodiment and 4 × 4 processors are used in the second embodiment, n × n processors (n and m are natural numbers) are used. It is clear that the present invention can be applied even when used, and in each embodiment, one pixel has 8 bits. However, the gist of the present invention is not limited to this number of bits. Further, the present embodiment is realized based on the two-dimensional XY coordinates, but it can be inferred that the present invention can be easily applied to the field of the three-dimensional graphics to which the Z coordinates are added.

[0040]

As described above, according to the present invention, both the straight line drawing function and the rectangular area transfer function depend on the number of processors to be used. The area transfer can improve the performance by the number of uses. Generally, in a multiprocessor system using a plurality of processors, the processing performance does not always increase in proportion to the number of processors used, and the hardware configuration tends to be complicated.
According to the present invention, the performance can be efficiently improved, and the hardware configuration can reduce the number of terminals for bus connection between processors by integrating a plurality of processors into one LSI, thereby reducing the cost. And high performance LS
I can be supplied.

[Brief description of the drawings]

FIG. 1 is a block diagram of a graphic drawing apparatus according to a first embodiment of the present invention;

FIG. 2 is a block diagram showing a configuration of a drawing engine of FIG. 1;

FIG. 3 is a configuration diagram of a memory in FIG. 1;

FIG. 4 is a coordinate diagram illustrating a straight line drawing.

FIG. 5 is a diagram illustrating a combination of connection between a memory and a drawing engine.

FIG. 6 is a view for explaining rectangular area transfer;

FIG. 7 is a block diagram of a second embodiment of the present invention.

[Explanation of symbols]

 1-4 drawing engine 5-8,65-68 memory 9 preprocessor 10 display processor 11 display 20 system bus 21-24,71-74 memory bus 25-30,75-80 processor bus 40 rectangular area transfer unit 41 Linear drawing unit 42 Memory interface 43 Switcher 50, 51 Bus 61-64 Processor module

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/06 520 G06F 9/38 370 G06F 12/00 580 G06F 15/16 610 G06T 11/00 100

Claims (1)

(57) [Claims] 1. A method in which a plurality of processors are simultaneously operated and X
In the graphic drawing apparatus that draws a graphic in a memory defined on Y information, each of the processors is allocated at least for every n pixels in the X direction and every m pixels in the Y direction for at least the straight line drawing function and the rectangular area transfer function. It is composed of n × m processors that operate to process every n × m pixels, and is allocated so as to be accessed every n pixels in the X direction and every m pixels in the Y direction, and stores pixel information respectively. and n × m pieces of memory modules, wherein each processor and the memory bus connecting between the respective memory module corresponding to each of these processors, and a plurality of processor bus that connects all between the respective processors wherein said one selected hand bus select and by a selection signal to connect said each processor of each memory bus the respective processor bus And when executing the line drawing function, the data transfer between the processors performed
Instead, when the selection signal is generated so as to calculate a straight line drawing and the rectangular area transfer function is executed, a processor connected to a memory storing transfer source data may be used.
Connected to the memory where the destination data is stored
Via a dynamically changing processor bus to the processor
And to forward the destination data, the destination data to the raster operation between the source data, with a selection control means for dynamically changing said selection signal for each said each processor A graphic drawing device characterized by the above-mentioned.