JPS6020383A - Magnetic bubble memory - Google Patents

Abstract

PURPOSE:To facilitate the recovery of information in a power-off state by providing a segment area with a block containing defective information and inhibiting information transfer between the block and a cache area in normal access. CONSTITUTION:Every segment of a magnetic bubble storage area is provided with a block such as the 8th block containing defective information which is discriminated by different flag information of the 1st loop, and information transfer between this 8th block and cache area is inhibited in normal access. When some segment is present in the cache area during initialization in power- on operation, defective information is erased in the cache area and stored to another storage element, only the information in the block 8 containing the defective information is transferred, and a segment address is read out to initialize a segment address counter. Then, the contents of the cache area and storage area are both recovered. In this case, even if the information in other storage elements are destroyed due to power-off operation, the information is recovered easily by the block 8 in the segment.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to address control of a magnetic bubble memory device having an on-chip cache configuration, and particularly to initial setting of the address of a control circuit when power is turned on.

In a magnetic bubble memory device, it is necessary to initialize the control circuit in order to synchronize the control circuit with the position of the bubble in the magnetic bubble memory chip when the device is powered on.

FIG. 1 is a block diagram of a magnetic bubble memory element having an on-chip cache configuration. In a magnetic bubble memory element with an on-chip cache configuration, bubble information is identified by two addresses. One address is an address for identifying bubble information in the cache area 101, and the cache loop 102, 103, 104, 105, 106,107
It is defined as a unit of 10 B (hereinafter referred to as a block) of bubbles located at the same position. This is called a block address. In the example of FIG. 1, one block consists of n pieces of bubble information. The other address is an address for identifying bubble information in the storage area io9, and is an address for identifying bubble information in the storage loop 110, 111, 112, 113, 114, .
A set of bubbles 116 (hereinafter referred to as a segment) located at the same position of 115 is defined as a unit. This is called a segment address. The segment 116 has the same size as the blocks that can be stored in the cache area 101, and in the example of FIG. 1, the segment is made up of eight blocks. Access to blocks in the on-chip cache configuration is performed as follows. The segment containing the block you want to access is stored in storage area 109 and cache area 1.
storage area 10 through a transfer gate 117 connecting
9 to the carriage area 101. Next, the block to be accessed is replicated or transferred to the major line 119 via the replicate transfer gate 118, and a write or read operation is performed.

In order for the above-described operation to be performed normally, a block address counter and a segment address counter are required to know the position of the segment in the storage area 109 and the position of the block in the cache area IQ1 when the device is powered on, and to control the address. It is necessary to initialize.

To achieve this, a method is used in which address information is written in a specific loop. Also, it is necessary to write defect information in order to control the defect loop. FIG. 2 is a diagram showing a conventional method of storing address information and defect information in the magnetic bubble memory device shown in FIG. The first loop stores a marker bit indicating the beginning of the block within the segment, and the second loop stores a marker bit indicating the beginning of the block within the segment. The fourth loop is stored. Conventionally, the m-period setting at power-on was performed as follows.

When the power is turned on, if the cache area IO1 does not contain any fragment, the storage area 1090 times 11t@ is transferred to the cache area 101 via the transfer gate 117. At this time, since the delimiter of one segment is not known, one segment's worth of bubble information must be transferred to the cache area 101 so that the marker bit indicating the beginning of the block and defect information are included. The block address can be found by searching for the marker pin (Y) of the segment that has entered the cache area, so the block address counter can be initialized.

Furthermore, by reading the segment address information, the segment address of the storage area can be found, so the segment address counter can be initialized.

The segments transferred to the cache area 101 are returned to their original positions in the storage area, and the initialization of the control circuit is completed.

In this case, it is necessary to transfer the storage area and the cache area in units of segments, which has the drawback of taking time.

Control was sloppy because segment transfer was performed when the division of segments was not yet known.

Next, a conventional method for initial setting>L when any segment exists in the cache area when the power is turned on will be described. In this case, the block address can be immediately found by searching the marker bit of the segment in the cache area. To obtain segment address information of a storage area, it is necessary to read blocks within the storage area. In order to transfer a block in a storage area to a cache area, it is necessary to empty the corresponding block in the cache area.

In the conventional method, one block of data is temporarily stored in a non-bubble storage element such as a data buffer included in a peripheral circuit, the bubble information for that block is erased, and the block in the storage area is moved to an empty cache area. It was necessary to transfer to the block and read the segment address information. The read block must be returned to its original location in the storage area, and the erased information must be converted back to bubble information and stored in the original block. But bubble 1-l′
If the power is cut off due to an abnormal situation after erasing the first report and before writing the bubble information again, that data will be erased and cannot be restored.

This meant that the nonvolatility of bubble memory was incomplete, which was an important drawback.

The present invention has been made in order to solve the above-mentioned drawbacks, and each segment and cache area contains defect information, and when the power is turned on, transfer of the block containing the defect information between the storage area and the cache area is prohibited. This is an address control method for magnetic bubble memory characterized by:

The purpose of the vll of the present invention is to enable information that is temporarily stored in an element other than a bubble when a block of a storage area is transferred to a cache area to be easily restored even if a power failure occurs. be.

A second object of the present invention is to enable easy initialization of the control circuit even when no segment exists in a portion of the carriage.

The present invention will be explained by examples. FIG. 3 is a diagram showing a method of storing address information and defect/16 reports according to the present invention.

The magnetic bubble memory element shown in FIG. 1 is used as in the conventional case. The first loop contains a marker pit indicating a block storing defect information, and the second to fifth loops contain segment address information.

One piece of defect information is stored in each segment 4u and one piece of defect information is stored in the cage area. Stores defect information.

A block that is 100% prohibits transfer between the storage area and the cache area in normal operation. In other words, there is always a block containing defect information @ in the cache area. The initial setting of the control circuit according to the invention is carried out as follows.

At the time of initialization, if there is no segment in the cache area, the marker bit is searched, the block address counter is initialized, the block containing the storage area is transferred to the cache area, the segment address information is read out, and the segment Initializes the address counter. The block transferred to the cache area is returned to the storage area, and initialization is completed. In this case, since only one block is transferred, the time can be greatly reduced. Furthermore, since the segment delimiter is already known at the time the block address counter is initialized, the segment address counter can be easily initialized. If any segment still exists in the cache area at the time of initialization, the marker bit is searched and the block address counter is initialized as before, but when moving from the storage area to the cache area. The blocks to be transferred are limited to those containing defect information. The defect information in the cache area is erased, the corresponding block in the storage area is transferred to the cache area, the segment address is read out, and the segment address counter is initialized. The transferred block is returned to its original location in the storage area, defect information is written into the cache area, and initialization is completed. Even if a power failure occurs between erasing defect information in the cache area and writing it into the cache area again, the defect information cannot be reproduced because each segment contains defect information. It's easy to do.

Therefore, the non-volatility of the magnetic bubble memory device is maintained.

As explained above, if the address control method according to the present invention is used, a non-volatile complete 4i with short initialization time can be achieved! The effect is great because an air bubble memory device can be realized.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an on-chip cache type magnetic bubble memory device, FIG. 2 is an explanatory diagram showing a conventional method of storing information in a magnetic bubble memory device, and FIG. 3 is a diagram according to the present invention. FIG. 3 is an explanatory diagram showing a method of storing information in a magnetic coupler memory element. 101... Cache area, 102...
- 1st cash loop, 103...2nd cash loop, 104...3rd cash loop, 105...4th cash loop, 10
6...5th cash roof", 107...
... nth cache loop, 108 ... block, 109 ... storage area, 110 ...
・First memory loop, 111...Second memory loop, 112...Third memory loop, 113...
...Fourth memory loop, 114...Fifth memory loop, 115...Nth memory loop, 116...
...Segment, 117...Transfer gate,
118...Replicate transfer gate, 119.
...Major line. W Ward Agent Patent Attorney Uchiharaguchi ・ □□- Zuro (1) 1 Helmet Z Illustration Group

Claims (1)

[Claims] In a magnetic bubble memory device using a magnetic bubble memory element with an on-chip cache configuration, each segment cache area has a block containing defect information, and during normal access, there is a gap between the storage area of the block containing the defect information and the cache area. A magnetic bubble memory device characterized by prohibiting the transfer of.