JPS5810249A - Status career storage system - Google Patents

Abstract

PURPOSE:To store the status career at failure generation and to make retrieval of failure easy, even with the firmware stall due to the generation of failure, by interrupting the career status storage and detecting the maximum number of times designated for the status career storage number. CONSTITUTION:A remainder number register 30 stores the status career storage maximum number and at the operation, the residual number of times is stored. When the content of the register 30 is ''0'' via an output signal line 61 and ''0'' at a detection circuit 32, a signal line 64 goes to logical ''1'', and a signal line 51 goes to logical ''1'' with an NOR circuit 20. Then, since an output signal line 53 of a mode flip-flop 21 goes to logical ''0'', no instruction of write to a status career storage memory 25 and revision of an address register 22 are made. That is, the status career storage operation is interrupted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a state history storage method, and more particularly to a state history storage method for storing a history of internal states for tracing the operation of an information processing device.

Conventionally, as shown in FIG. 1, this glue state history storage system includes an instruction execution control circuit 1O, a state history storage memory 25, a NOT circuit 20, a mode flip-flop 21, and an internal state history storage memory 25, as shown in FIG. It consists of a status information register 24, a status history storage memory address register (hereinafter abbreviated as address register) 22, and a counter 23, and is configured to perform an I! For example, for each firmware step, the contents output from the instruction execution control circuit 10 and stored in the internal status register 24VCw1 are outputted to the total status history storage memory 25. At this time, the condition and other history Ne
The storage address to the t(a memo') 25 is given by the address register 22, and each time the contents of the internal status 1H information register 24 are stored in the status history storage memory 25, the contents of the address register 22 are stored from the counter 23VC. Z is updated and V' is set to point to the next address where the previous VCC was entered.
W'U h is copied, and h1 ≦ state is set as VC so that the state can be determined from address 11 (position) of the state history storage memory 25. In order to interrupt the trace when reaching Ic,) the race stop signal line 50 is set to logic ``l'' and the NOT circuit 20 turns logic ``ON'' to turn the mode free meso solo knob 2 to logic. ″0′ Kinki 1, chopsticks, result 1-L/
'-The space operation is aborted. -Signal 1i again! 52, by setting the mode flip 70 knob 21 to IJj '''l', it is also possible to open +jr for 1 race 1 oil 1. In this way, the internal state is agitated: I:tj L,
By keeping it in place, when a failure occurs, the information is dumped into the C+il N city's section 1 and used for disciplinary action.

However, the state of one's memory is limited, and one's memory is limited. The highest level address of 1 is 1; 1 is the highest address of 25, and 11 ≦ status information is 1.
i (Jt H address register 22hi 114)
114 History 11 Self-unique memory 25's tenth-(\γ address is pointed to, and the lowest address in history is VC
M+, memory f1. Since the contents of the at/sler raster 22 point to the next address from the counter 23VC, the state history storage memo') 25 VC storage i+-
, -The internal wide section information is l"Ill"↓V
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was. Because of this, the internal l of each stenog is 1/113b of tour unevenness! ν to I! (Full interpretation 1-ξHistory Kimi 1,
In the operation trace VC stored in the memory 25, due to a fault, the firmware stalls and the h race (l' stops).
K No. 50 (because it did not occur, state history memory memo IJ
By successively storing the execution states of stalled firmware instructions, the stored internal state at the time of failure is often lost.

[]R of the present invention, the set state history record 1jt maximum number of times is violated, but the new state 1 history record operation 11) There is no indication of opening, and the execution of firmware 16 continues. At the time, the internal state at the time of the occurrence of the previous layer is saved by checking the previous layer's defects 1-1. It's about doing.

According to the present invention, the state history δ1 according to the VC is stored using a storage means for storing the maximum number of times, a counting means for storing the entire internal state of the device, and a counting means for storing the entire internal state of the device. The state history i05 detects that the number of times the history rhyme has reached the maximum number of times, and the output signal from the detection means and the previous detection means is interrupted. A state history storage method characterized by including all interruptions
4'i S Lu.

Next V'C% Check the details of the present invention and read the detailed information 1.

− Clarify. FIG. 2 is a block diagram showing one embodiment f+1 of the present invention, in which the state history storage method of the present invention includes a quality control circuit 10, a state decoy history storage maximum number of times, and a remaining number of times during operation. Remaining number of times register to store all: 30 and circle t41
Complete list of 5 states 1. Each time you do this, write it down in -.Remaining number of times register 30
A counter 31 for subtracting the contents of 1 by 1, and a circuit 32 for displaying all images to indicate that the contents of the remaining number of times register 30 have become '0'.

N01 to circuit 20, mode door 1J knob 70 Noah' 21, state history memory 25, address register 22, counter 23 for adding 1 to address register 22 to 1u for storing internal state, The register 24 is composed of an inner M-shaped register 24.

Next, I will explain the entire structure of the above structure.

Address register 2 at initialization of information processing device 1
2 is the state (the lowest 1\γ address of the memory 25 is set to '0'), and the 7-Dofflinog flop 21 is connected to the 16th line 52 from the 1till ω1j circuit 10. VCu: logic [Remaining number of times register in ψ'1': 30 kemeisha' central row it'll il + circuit], initialize all bits to logic '1' by signal line 60-5- from O .

'''0' output circuit 32rj: When the content of the remaining number of times register 30 reaches logic ``0'' 71\[7, no output circuit 2o
Logic ``1'' is output to the signal line 64 to . '-1: taN
O circuit 20V (inputs the history stop signal line 50 from instruction/actual control f11 route 10, and when both signal line 5o and signal line 64 are at '0', output signal from NO14 circuit. The pin 51 becomes logic 11', and the mode flip-flop 21 becomes logic 'l'. When the mode flip 70 knob 21 is logic %lI, writing to the state history memory memo 1J25 and changing the address register 22 [instructs The signal line 56 is connected to the signal line 56 from the Kinuta-Imai row control circuit IO.
The output information of the contents sent to the status information register 24 is sent to the status history storage memory 25 via the line 57, written to the address indicated by the address register 22, and further written to the status history storage memory 25VC. , the contents of the address register 22 are updated by the counter 23 and written to the address register 22VC again.

At the same time (yC, ffJ instruction execution 'tIjlJ 1+1
The contents of the remaining number register 30 are updated by the counter 31 according to the double--6- dark line 60 from the circuit 10, and are written to the remaining number register 30 again. When the 10' detection circuit 32 detects that the content of the remaining number of times register 30 has become 0' via the output signal line 61, the signal line 64 becomes logic '1', and the NOR circuit 20 causes the signal line 51 to become 0'. becomes logic 1', and the output signal line 53 of mode flip-flop 21 becomes logic 1:! li'
Since the value becomes o', instructions for filling the state history storage memory 25 and updating the address register 22 are no longer performed.

That is, the state history storage operation is interrupted. Here, the remaining register 30 is connected to the signal line 60 from the instruction execution open side 1 circuit 10.
The state history storage operation can be restarted by resetting all bits of Jl to logic Jl. Also.

The mode flip-flop 21 is set to logic l' by the output signal line 52 of the instruction execution control circuit 10.

Condition history 1. can resume operation.

A configuration like the above! In the h11 work, the number of bits in the remaining number of registers 3017) is n, the number of bits in the address counter 220 is In, and the explanation continues with explanation 1 assuming that n≧n]. The state history storage memory 25 can store all internal state information for 2m steps at a time, and unless restarting the state history storage operation is instructed by the signal line 60 of the command execution control circuit IO, the state history operation for one step will not be executed. Analyze the first year of middle school.

This more JJ + combination, 2n in the firmware instruction
The remaining number of times register 30 is sent from line 16 0VC of the instruction execution control circuit 10 every time the number of execution steps is determined in the following intervals.
All pit money logic 11' is reset. By doing the above, if the firmware stalls due to an infinite loop or event waiting loop due to a failure, etc., the remaining number of times register 30 will be set to 101.
Next door.

'0' +fi: The storage operation of the state history continues until the output circuit 32-C'o' is detected, but when '0' is detected, the output signal line 64 of the output circuit 32 becomes logic 1
1', the state history storage operation is interrupted, and no instruction is issued via the instruction execution control circuit lot/) signal line 60 to reset all the pits in the remaining number register 30 to logic '1'. Therefore, the internal state of the information processing device 1 at the time of failure is preserved.

In the above explanation, it is clear that the same operation as above is possible by using the borrow/carry detection means in the counter 31 instead of the %'01 (blowout circuit 32).

Furthermore, the settings to be set in the remaining number register 30 are not limited to all bit logic ``''l'', and it can be easily inferred that any variable can be set at any timing by instructions from the instruction execution control circuit 1 (1). Ru.

As described above, the present invention is configured to detect that the number of times the state history is stored has reached a specified maximum number of times and to interrupt the state history storage.

Even when the firmware is stalled due to the occurrence of a fault, the state history at the time of the fault can be stored, which has the effect of facilitating troubleshooting.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional state history storage device.
The figure is a block diagram of one implementation of the present invention. =9- 1...Information Center 8! Interposition, 10...Instruction execution side part, 20...N O'J' circuit, 21...Mode flip-flop, 22
... Address register, 23 ... Counter, 24 ... Internal state information register, 25.
...Status history storage memory, 30...Remaining count register, 31...Color/re, 32...
...'0' detection circuit. 10-

Claims (1)

[Claims] A storage means for storing the maximum number of times the state history is stored, a 1F number means updated every time the internal state of the device is stored, and a means for counting when the number of times the state history is stored reaches the maximum number of times the state history is stored. (A state history storage system characterized by comprising: a detection means for detecting the data; and an interrupting means for interrupting state history storage using an output signal from the detection means.