JPS60202966A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To perform solder connection without deviation of electrodes and electrode plates, by the processes of position alignment of the electrodes of a semiconductor element and the electrode plates supported by a supporting plate, the process of heating and fusing of the solder, the process of removal of the supporting plate, and the process of reheating and fusing of the solder. CONSTITUTION:A cathode electrode plate 3 and a gate electrode plate 4 of a compound electrode 20 and a cathode electrode 13 and a gate electrode 14 of a GTO thyristor element are aligned at respective corresponding positions. The device is heated in a reducing atmosphere. A solder layer 5 is fused. Both electrode plates 3 and 4 of the compound electrode 20 and the GTO thyristor element are connected by the solder. In the compound electrode 20, the supporting plate 1 and the electrode plates 3 and 4 are stuck by an epoxy bonding agent 2. Therefore, the plate 1 is mechanically separared and removed after heating. After the supporting plate 1 is separated and removed, the solder is heated and fused again, and the deviation of the positions of the electrode plates 3 and 4 is corrected.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device, particularly a GTO (gate turn-off) in which one main electrode and a control electrode are formed on the same main surface.
Related to manufacturing methods of semiconductor devices such as thyristors and transistors.

[Background of the invention]

Figure 2 shows the structure of a conventional GTO thyristor. In the figure, 100 indicates p emitter pg, n base nJI,
A semiconductor substrate 101 consisting of semiconductor layers of a p base 9m and an n emitter n, a cathode electrode 102 ohmically connected to the n emitter r1g, and an ohmically connected to the p base 9m exposed on the same surface as the exposed surface of the n emitter nB. This is a GTO silice element consisting of a control electrode, that is, a gate electrode 103, and an anode electrode 104, which is the other main electrode, which is ohmically connected to one p-emitter layer.

As shown in the figure, the nLc emitter ng is connected to the gate electrode 103.
The npnp region including the n-type ivy nIB arranged in an island shape surrounded by the gate electrode 10 is the operating region.
The pnp region containing 3 is the control region. The purpose of this arrangement is to efficiently cut off large load currents. In other words, by surrounding the elongated emitter with a gate, the distance between the gate and the region furthest from the gate within the emitter and the distance between the gate and the region closest to the gate can be minimized, and the turn-off signal from the gate can be distributed within the operating region. Make it work effectively throughout.

At the same time, by arranging a large number of these n emitters, the overall operating area is enlarged and the current capacity of the element is increased. ``By increasing the current capacity and narrowing the widths of the cathode electrode 102 and gate electrode 103, it is possible to efficiently interrupt the load current. For example, the width of the electrodes is 50 to 500 μm, and the spacing between their electrode centers is 30 to 500 μm.
It is often formed to a thickness of 300 μm. Cathode electrode 102 and gate electrode 10 of GTO thyristor element base 100
3, both electrode plates 108 and 109 of a composite electrode material 200 in which a sword electrode plate 108 and a gate electrode plate 109 are integrally formed on the surface of an organic insulating film 2010 are attached to a solder layer 1.
They are connected to each other via 10. Note that 108B and 109B are common connection portions for collectively connecting the corresponding electrode plates 108 and 109i, respectively, to external lead wires and the like. When a turn-off signal is applied, a voltage drop occurs in the longitudinal direction of the gate electrode 103 due to the current flowing in the longitudinal direction of the gate electrode 103, and this voltage drop causes uneven turn-off operation in each operating region. There is a drawback. However, by appropriately selecting the thickness of the electrode plates 108 and 109 formed in the composite electrode material 200 and increasing the thickness of the electrode plates, the resistance in the longitudinal direction of each electrode plate can be reduced and the above-mentioned drawbacks can be improved. I can do it. As a connection method of the electrode plate in a GTO thyristor with this structure, rj, , GTO
A solder is interposed between the thyristor element 100 and the composite electrode material 200 to align the two, and the solder is melted by an arbitrary heating source to connect them all at once.

Here, the organic insulating film 201 prevents deformation of the elongated and independent cathode electrode plate 108 and gate electrode plate 109, supports both on the same surface, and supports the cathode electrode 102 and gate electrode 1 on the semiconductor substrate 101.
This is for connecting to 08 at once. On the other hand, the cathode electrode 1 formed on the GTO thyristor element 100
03. It is possible to solder the anode electrode 104,
A metal film that easily makes an ohmic connection with the semiconductor substrate 101 is used. At-Ni-Ag, Cr-N1-Ag
A typical example of this is a multilayer metal film of Cr-Cu-Au.

In order to further increase the current capacity of a semiconductor device having the structure described above, it is necessary to arrange a large number of n emitters,
In order to increase the current capacity of the device, as described above, the widths of the cathode electrode 102 and gate electrode 103 and the distance between the electrodes must be made as narrow as possible.

A semiconductor device structure such as the GTO thyristor shown in FIG. 1.2 has the following drawbacks.

Generally, the organic film 201 supporting the electrode plates 108 and 109 of the composite electrode material 200 is made of polyimide, polyester, or the like. The coefficient of thermal expansion of the semiconductor element 1
It is one or more digits larger than 00. In a semiconductor device having the solder connection structure shown in Fig. 1-2, the temperature of the semiconductor element increases due to the load current flowing during operation, and this causes the semiconductor electrode surface with small thermal expansion and the organic Due to the difference in thermal expansion of the film 201, thermal stress is generated in the solder layer. This generates thermal stress in the solder layer, which greatly impedes the reliability of the semiconductor device.

In addition, the organic film 20 with large thermal expansion as described above may be used.
1, the following drawbacks also occur when attempting to arrange a large number of n emitters in order to increase the current capacity of the GTO thyristor.

FIG. 3 is a diagram for explaining the problem when a large number of n emitters are arranged to increase current capacity. The figure shows a partial view of the solder connection between the composite electrode material 200 and the GTO thyristor element 100.

Generally, solder connections are made by heating and melting the solder material depending on its melting point. Here, the composite electrode material 200 is an organic insulating film 201 that supports the cathode electrode plate 108 and the gate electrode plate 109, and when heated, expands according to the heating temperature. Accordingly, the cathode electrode plate 108
, the gate electrode plate 109 is the GTO thyristor element 100
Misalignment occurs with respect to the cathode electrode 102 and gate electrode 103 above. In other words, cool down and complete the solder connection.
However, when the solidification temperature of the solder 10 is reached, the composite electrode material 200 expands by that temperature, and the cathode electrode plate 108, the gate electrode plate 109, and the cathode electrode 102,
It is fixed to the gate electrode 103 with solder,
As a result, positional deviation occurs. For this reason, the structure is such that adjacent electrodes are intertwined with each other, like a bridge island or interlocking comb teeth, and a large number of emitters are arranged to expand the current. If you try, it will occur noticeably. Furthermore, this tendency becomes more pronounced toward the ends of the semiconductor substrate 101.

When such a bridge a occurs, for example in the case of a GTO thyristor as shown in Fig. 1, a current flows directly from the cathode, that is, the n emitter n1, to the gate, that is, the p base p11. You may not be able to pull out the carrier.

Another problem is that even if the bridge shown in FIG. 3 does not occur, the electrode plates 108 and 109 may be misaligned with respect to the electrodes 102 and 103, causing the solder material to be attached to the electrode plates. They are not connected uniformly to each other, but are biased to one side as shown in FIG. In a semiconductor device having a solder connection structure, the temperature of the semiconductor element increases due to the load current flowing during operation, and this causes a difference in thermal expansion between the electrode surface of the semiconductor element, which has a small thermal expansion, and the extraction electrode, which has a large thermal expansion. This causes thermal stress in the solder layer of the connection.

For this reason, if the solder is biased to one side due to the positional shift of the electrode plate, thermal stress will be concentrated in that area, causing cracks and the like, which will seriously impede the reliability of the semiconductor device.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a semiconductor device in which solder connections can be made without sacrificing the performance or reliability of the semiconductor device.

[Summary of the invention]

The present invention involves aligning the electrodes of a semiconductor element and an electrode plate supported by a support plate, heating and melting the solder, removing the support plate, and reheating and melting the solder. This corrects the misalignment and achieves the object of the present invention.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using examples.

FIG. 5 shows a composite electrode material 2o and a semiconductor element 1o used in the example. The composite electrode material 2o is made by pasting a support plate 1 made of polyimide film with a thickness of 75 μm and an electrolytic copper foil with a thickness of 35 μm on the lower surface of the support plate with an epoxy adhesive 2 having a thickness of 20 μm, and then forming a cathode with a width of 180 μm. Electrode plate 3 and width 1
A gate electrode plate 4 of 20 μm is patterned. The electrode plate 3.4 is plated with a solder layer 5 having a thickness of 25 μm. In the embodiment, the cathode electrode plate 3 is 2
The number of gate electrode plates 4 is 21, and the gate electrode plates 4 are patterned so as to surround the cathode electrode plates 3.

The uppermost layer is made of Ag, and a cathode electrode 13 with a width of 280 μm and a cathode electrode 14 with a width of 220 μm of a multilayer metal film of Cr-Ni-Ag are formed to form a GTO thyristor element L groove, and the electrode center spacing is 300 μm. It is. The number corresponds to and is the same as the electrode plates 13 and 14 of the composite electrode material 20. In addition, GTO Cyrisk element 10
is the size of 1o order x 20m.

FIG. 6 is a diagram showing a process of soldering the above-described composite electrode material 2o and GTO thyristor element 1O. Figure 6 U
) shows a state in which the cathode electrode plate 3 and gate electrode plate 4 of the composite electrode material 2o are aligned with the cathode electrode 13 and gate electrode 14t of the dTo thyristor element in corresponding positions, respectively. Fig. 6 0) is heated in a reducing atmosphere to melt the solder layer 5 and connect the composite electrode material 200, both electrode plates 3.4 and GT.
This is a solder-connected O thyristor element. At this time, the composite electrode material 20 begins to expand as it is heated. After melting the solder layer 5, when cooling begins, the solder layer 5 solidifies. At this point, both electrode plates 3.4 are fixed and connected with the solder layer 5. That is, the connection is made by solder in a state where the position is shifted by the amount of expansion of the composite electrode material 20 with respect to the temperature of the solidifying point of the solder. For this reason, a positional shift of the electrode plate 3.4 with respect to the electrode 13.14 and a solder bridge occur as shown in FIGS. 3 and 4. FIG. 6(3) shows the step of peeling off and removing the polyimide film support plate 1 of the composite electrode material 20 after soldering. Composite electrode material 2 used in this example
0 is a support plate 1 with an epoxy adhesive 2 as described above.
and electrode plates 3 and 4 are bonded together. The adhesive force of this epoxy adhesive 2 is reduced by heating during solder connection, and it can be easily peeled off, and in this example, it was mechanically peeled off and removed. (4) After peeling and removing the support plate 1, the solder is reheated and remelted to form the electrode plate 3.4.
This shows the state in which the positional deviation of has been corrected. Figure 6 (2)
The electrodes 3 and 4 are expanded by the expansion of the composite electrode material 20.
If the electrode plate 3.4 is misaligned with respect to the electrode 13.14, it can be fixed by reheating and remelting the solder layer 5. Due to the surface tension of the solder layer 5, the electrode plate 3.4 can be stretched to the approximate center of the electrode 13.14. and its position can be corrected.

In the composite electrode material configured as in this example, the support plate l
Particular consideration must be given to the expansion of polyimide films as the temperature increases. That is, this is because the expansion coefficient of the polyimide film is sufficiently large compared to the semiconductor substrate, electrode plate, etc. constructed in this example. FIG. 7 shows actual measurement of positional deviation between the conventional method and the present invention. According to the figure, in the conventional method, the positional deviation at the extreme end reaches approximately 40 μm. Conversely, according to the present invention, it is 5 μm or less.

Note that for the semiconductor device shown in this example, -55C
- When a temperature cycle test was carried out for 1000 cycles in which one cycle was from room temperature to 150C, no abnormality occurred in the solder connection layer.

In the above embodiments, the case where the present invention is applied to a GTO thyristor has been described, but the present invention is not limited to this, and can be applied to other semiconductor devices such as transistors that turn on and off a load current according to a control signal. It is clear that the same can also be applied. In addition, in the examples, solder plating was used as the method of supplying the solder material, and Pb-
Although 51Sn solder was used, the present invention is not limited to this.

In addition, in this example, the electrode plate of the composite electrode material was used by applying solder plating in advance, but there is no effect even if solder is formed on the electrode on the semiconductor substrate in advance and the composite electrode material is connected by soldering. does not change.

As illustrated in FIG.
8 is mounted on the electrode plate 3゜4 is the auxiliary support plate 402
A brazing material 40 is placed above to surround the GTO thyristor element 10.
There is an example in which the alumina plate 404 provided in step 5 is fixed via a solder 403, covered with a silicone resin 406, and then sealed with a cap 409. In such a case, the soldering process is the same as described above. Since the solder remelting process is carried out at the same temperature as the solder remelting process after removing the support plate, the solder connection process during packaging and the solder remelting process for correcting positional deviation can be combined.

〔Effect of the invention〕

As explained above, the manufacturing method of the present invention can correct the misalignment of the solder connection between the electrode plate supported by the composite electrode material and the electrode of the semiconductor element, without impairing the performance and reliability of the semiconductor device. .

[Brief explanation of drawings]

Figure 1.2 shows the structure of a conventional GTO thyristor.
Fig. 1 is a plan view, Fig. 2 is a sectional view taken along the line A-A in Fig. 1, Fig. 3.4 is a partial sectional view of the GTO thyristor showing the drawbacks of the conventional example, and Figs. The figures are diagrams for explaining one embodiment of the present invention; FIG. 5 is a partial cross-sectional view showing the structure of the GTO thyristor and composite electrode material; FIG. 6 is a cross-sectional view showing the electrode connection process; and FIG. 8 is a diagram illustrating a detailed explanation of the present invention, and FIG. 8 is a diagram showing an application example of the present invention. l... Support plate, 2... Adhesive, 3... Cathode electrode plate, 4... Gate electrode plate, 5... Solder layer, 10
...GTO thyristor element, 13... cathode electrode, 14... gate electrode, 20... composite electrode material°. Agent Patent Attorney Akio Takahashi f1 diagram / 1112 ¥ 2 diagram μ elephant J Metomi 5 diagram 'Jrt Figure (2) Mei 7 diagram (SuJmu・Iku) ga-1-tjk /l 411 f
(yptm) 18 figure dat yiy #7 (dllll

Claims (1)

[Claims] 1. It has a pair of principal optical surfaces, a predetermined pn junction is formed on the principal surfaces, and one principal optical surface has a plurality of operating regions and a control region adjacent thereto. A semiconductor element having one main electrode and a control electrode provided on the surface of an exposed semiconductor substrate and a plurality of operating regions, and a main electrode plate and a control electrode that are aligned with the main electrode and the control electrode, respectively, and connected by solder. Using a composite electrode material integrally formed on a support plate, a plurality of main electrodes and control electrodes of the semiconductor element and a plurality of main electrode plates and control electrode plates of the composite electrode material are connected via a solder layer. A semiconductor device manufacturing method 2, characterized in that after aligning and melting the solder, the support plate is removed from the main electrode plate and the control electrode plate, and then the solder is melted again, in claim 1 A method for manufacturing a semiconductor device, characterized in that a main electrode plate and a control electrode plate are integrated with a support plate using an adhesive that deteriorates with heat.