JPS6020266A - Memory control system - Google Patents

Abstract

PURPOSE:To obtain high speed of access time of an intermediate buffer memory by deciding whether an access of the intermediate buffer memory can execute or not and retrieving an address array of the intermediate buffer memory at the same time. CONSTITUTION:The request from CPUs 103 and 104 and input/output channel 105 is sent to a intermediate buffer memory 102, and each request is set to a request register 202. The set request is set to a WAA retrieval request register 206 through a priority circuit 204, and is stored in the WAA209. The registered address, which is read from the WAA209, is inputted to the comparison circuit 213, and coincidence with the request address is checked. At the same time, whether the request address is already interlockecd by other units or not is checked in a comparison circuit 212. A decision circuit 216 decides access approval of an intermediate buffer memory 102.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a memory control method, and particularly to a main memory (hereinafter referred to as MS).
This is a so-called three-level memory system that has a medium-speed intermediate buffer memory (hereinafter referred to as WS) between the high-speed buffer memory (hereinafter referred to as BS) in the arithmetic processing unit (hereinafter referred to as CPU). The present invention relates to a memory control method in a system in which a WS is shared by multiple CPUs and a traffic channel (hereinafter abbreviated as CH).

[Background of the invention]

FIG. 1 shows an example of the Bell memory system, in which two (1) CPUs 103 and 104 and 1o5cH share 102 WS.

Now, when 103 CPUO wants to read data ao, 10
6 BS That continues from there, if 106B
If not, send a 102W request to S.

102 WS, line AJS 102 including 3G
If there is 1C in W S, read it from there and get 103 CP
[J □ or if not reappointed, 101 M
Request +b to S, read line A from 101 M S, interrupt to line A and 102 WS, and aof
103 Transfer to CPU O.

The purpose of installing the 102 WS is as follows. 103,104 Contrary to the recent remarkable trend in the number of logic elements used in CPUs, the large memory elements used in the 101M5 are Although there has been significant progress in improving the collection rate, there has been little improvement in terms of access time and cycle time.WS is installed to bridge the speed difference between the CPU and MS.

By the way, one of the factors that hinders high-speed access to WS is
One example is interlock. As is well known, an interlock is an attempt by a certain device to use memory data at a certain address exclusively, and the device is not allowed to access an address that is interlocked by a certain device. .

Even in WS, this situation is no different.

In other words, the WS cannot be accessed unless fn is checked to see if the ink lock is applied by another device. This is one of the factors that increases the access time of the WS as viewed from the CPU and CH, and is an issue in preventing an increase in the access time of the WS by supporting the interlock device WVjt of the present invention.

[Embodiments of the invention]

FIG. 2 shows an embodiment of the invention. Items with the same reference numerals as in FIG. 1 are the same products.

103.104 Requests from CPU U and 105 CH are sent to 102 via 201 request 1ld31.
The data is sent to the WS and set in the request register 202, respectively.

The requests set in the request register 202 are inputted to the priority circuit 204 through the line 203, where a predetermined algorithm takes the priority among the requests, and the selected request is sent through the line 205 to the 2Q5WAAfi search request register. is set. 206 W A A crossbar and register set request is WS address array 209W
Read AA. W A A read from 209 WAA
The registered address of conveyor circuit 21 is specified by spelling 211.
3 and is checked for address match in the conveyor circuit together with the request address input via line 207.

213 When a match of addresses is detected by the conveyor circuit and the data of the address or black in the WS is found, the 21
The 5INW8 signal becomes '1''.

Incidentally, the request address of gland 207 is also input to the conhair circuit 212. The other input line 210 of the 212 conveyor circuit is the 20
This is the output of 8 LAA yQ) et al. 208LAA
112 is a lock address array that remembers the address that currently has the interlock set and the interlocked device.
Using the request address inputted by step 07 and numbers 1j and 1 that identify the requesting device, it is checked whether the request address has already been interlocked by another device.

If the ink clock is not set by the request or by another device, 214 Not I NLA
4 signals are output.

216 WS access liver leg circuit has ffM2O
Request address by 7 and IN by m215
WS signal, Not xNi by i 214, AAi=
-The way I put it in is wrong. If both the I N W S I 100 and Not I N LAA signals are 11", access to the WS is permitted. 218 WS access registers correspond to banks of WS, and here, 21
An example of four 9vvS banks is shown.

When the 216 WS access permission determination circuit permits access to the arm S, the address necessary for the WS access is sent via the line 217 to the 218 WS access register of the WS bank determined by the request address.
Write data, operation type signals, etc. are set, and access to the WS is started.

〔Effect of the invention〕

From Fig. 2 and the operation in Fig. 2 already explained, it is clear that μ
When a request is made to a WS, the request address has already been in-locked by another device, and the determination as to whether or not the WS cannot be accessed is made at the same time as the WAA search.

Since the WAA is an address array that handles a large number of entries, it is usually created using an extremely high-speed memory element.

However, since the LAA has a small number of end IJs, it is quite possible to construct the IJ with a single buried element.

Therefore, within the time it takes to remove the WAA and detect the address match (checking whether C is set by the ink clock by the optical 212 conveyor circuit or by another device is completed. While checking the WAA, it was found that the check to see if the request address was set as an inklock by another device71) was completed, and the access time of the WS was cooled due to the interlock. I understand that there is nothing to do.

[Brief explanation of drawings]

Figure 1 shows a 3-level memory configuration with multiple C
FIG. 2, a system configuration diagram shared by P[J,C)I, is a block diagram of an embodiment of the present invention. 201...Request set 202...Request register 209...WAA 207...Line 212...Conveyor circuit O Cρυ0 □ fZ diagram

Claims (1)

[Claims] 1. A memory system consisting of a low-speed, large-capacity main memory, a medium-speed, medium-capacity, intermediate buffer memory, and a high-speed, small-capacity buffer memory in an arithmetic processing unit, wherein the intermediate buffer memory is connected to a plurality of arithmetic processing units, In a system shared by channel devices, for a request to the intermediate buffer memory, the address array of the intermediate buffer memory is searched and the requested address is already interlocked by another device and checked whether it cannot be accessed or not. By doing this, the arithmetic processing unit,
1. A memory control method, characterized in that the overhead time required for checking the interlock in the access time of the intermediate buffer memory from a channel is eliminated, and the access time of the intermediate buffer memory is accelerated.