JPH0498343A - Memory control system - Google Patents

Abstract

PURPOSE:To ensure the consistency of data and to convert partial writing into whole writing by merging a write address write data of a processor, writing all data in a main storage device and invalidating data on the address of the other processor. CONSTITUTION:There is a case when the write address at that time does not exist in a buffer storage device 7a which is to execute writing and the address exists in the other buffer storage devices 7b and 7c as the write address from the processor to which the address applies. In such a case, data written in the main storage device 5 is transferred to the buffer storage device and transferred data and write data at that time are merged so as to write them in the main storage device 5. Furthermore, data on the addresses to which the other buffer storage devices 7b and 7c are applied are invalidated. Thus, different data are prevented from existing in plural buffer devices. Thus, the consistency of data between plural buffer storage devices is ensured and partial writing is converted into whole writing in all the cases.

Description

[Detailed Description of the Invention] [Summary] Regarding a memory control method that converts a partial write to a main memory device into a full write, the present invention guarantees data consistency between multiple buffer storage devices,
and for the purpose of converting a partial write into a full write in all cases, at least one main memory, a plurality of processors,
In a memory control method comprising a plurality of buffer storage devices corresponding to the plurality of processors, and in which the relationship between the main storage device and the buffer storage device is managed in a store-through method,
When a write request is issued from a processor, if the write address exists in the buffer storage device of the processor in an exclusive state, the data at the corresponding address in the buffer storage device and the write data of the processor are merged and stored in the main memory. When all writes are performed to the device and the write address exists in a shared state among multiple processors, the data at the corresponding address in the buffer storage device of the processor that issued the write request is merged with the write data and stored in the main memory. All writes are performed, the data at the corresponding address in the buffer storage device of a processor other than the processor that issued the write request is invalidated, and if the write address does not exist in the buffer storage device of the processor concerned, the data in the main storage device is invalidated. The data at the corresponding address is transferred to the buffer storage device for writing, the transferred data and the processor's write data are merged and all written to the main storage device, and the data at the corresponding address in the buffer storage device of another processor is merged. Configure to invalidate data.

[Industrial Application Field] The present invention relates to a memory control method that converts partial writing to a main memory device into full writing.

[Conventional technology]

Store-through and store-in methods are known as memory control methods for computer systems consisting of multiple processors.

The store-through method is a method in which data is written to both main memory and buffer storage when there is a write request from the processor.The feature of this store-through method is that the latest written data is always stored in the main memory. Therefore, even if a failure occurs in the buffer storage device, the data can be reliably preserved and a system with high reliability can be constructed.

However, in the store-through method, each time a write request from a processor occurs, a write is performed to the main memory, so in a system where one main memory is shared among multiple processors, the main memory The disadvantage is that the busy time of the system becomes longer and the system performance deteriorates.

On the other hand, in the store-in method, when a write request is issued from the processor, data is normally written only to the buffer storage device, and the data block stored in the buffer storage device becomes a new data block. Only when replaced is the data being replaced written to main memory.

Therefore, in the store-in method, the frequency of access to the main storage device is reduced, so the busy state of the main storage device is shortened, and system performance can be prevented from deteriorating.

However, the store-in method has the drawback that the latest data exists only on the buffer storage device, so if a failure occurs in the buffer storage device, the latest data will be lost.

[Problem to be solved by the invention]

Therefore, in the store-through method described above, if it is possible to keep the main storage device busy while writing data to the main storage device, a highly reliable and efficient system can be constructed.

Generally, writing data to main memory requires error checking and correc- tion.
(rection) code is added in units of a predetermined number of bytes (this is called an ECC unit, for example, in units of 8 bytes). When writing data from the processor that is shorter than the ECC unit (for example, 4-byte data), it is a partial write, and the data in the ECC unit is first read from the main memory, and the data written by the processor is merged with the read data. Data is written in the following steps: after that, an ECC code is created, and the data in the created ECC unit is written to the main storage device.

That is, partial writing requires two operations, one for reading and one for writing, to the main memory, increasing the number of accesses, which causes the busy time of the main memory to become longer.

Therefore, various methods have been proposed for converting partial writing into full writing. For example, Japanese Patent Laid-Open No. 137440/1989 discloses a technique for converting partial writing into full writing in a single processor system. .

However, this proposal does not solve the problems that arise in multiprocessor systems. In a multiprocessor system, one processor's write address may be held in the buffer storage of another processor because multiple processors write data to their respective buffer storages. Therefore, when writing data, it is necessary to ensure consistency of data between a plurality of buffer storage devices.

For example, JP-A-51-38839, JP-A-55-33
No. 253 describes a technique for converting a partial write into a full write when a main memory is shared by a plurality of processors.

However, neither technique has been able to convert partial writing into full writing in all cases while maintaining consistency of data in a plurality of buffer storage devices.

It is an object of the present invention to guarantee data consistency between a plurality of buffer storage devices and to be able to convert a partial write into a full write in all cases.

[Means to solve the problem]

FIG. 1(a) is a diagram explaining the principle of the present invention. Furthermore, FIG. 1 et al.) are diagrams illustrating the system configuration of a multiprocessor system based on the memory control method of the present invention.

The multiprocessor system according to the present invention includes at least one main storage device 5 (see FIG. 1 et al., the same applies hereinafter),
A plurality of processors 6a, 6b, 6C and a plurality of buffer storage devices 7a, 7b corresponding to the plurality of processors.
, 7C, main storage device 5 and buffer storage device 7
A to 7C are managed using a store-through method.

Further, the storage control device 8 shown in FIG. This storage control device 8 has a TAG section 8a that stores copy information of part or all of the address information of each buffer storage device 7a to 7c.

When a write request is issued from the processor 6a, 6b, or 6c, there are the following three states of the addresses registered in each of the buffer storage devices 7a to 7c.

(1) When the write address exists in the buffer storage device of the processor in an exclusive state.

Here, the exclusive state is, for example, a case where the address exists as a write or read address from the processor 6a in the buffer device 7a to which writing is to be performed, and does not exist in the other buffer storage devices 7b and 7c. In this case, the data at the corresponding address in the buffer storage device 7a and the write data are merged and all written into the main storage device 5.

(2) When the write address exists in a shared state among multiple buffer storage devices.

Here, the shared state means that, for example, the address is written to the buffer storage device 7a by the processor 6a.
This is a case where the address exists as a write or read address from the main memory device 5, and exists in the other buffer storage devices f7b, 7c as a read or write address from the main memory device 5. In this case, the data at the corresponding address in the buffer storage device 7a and the write data are merged and all written into the main storage device 5. Furthermore, the data at the corresponding addresses in the other buffer storage devices 7b and 7c are invalidated.

(3) The write address does not exist in the buffer storage of the processor.

In this case, the data at the corresponding address in the main memory unit W5 is transferred to the buffer storage device 7a to which writing is to be performed, for example, and the transferred data and write data are merged to write all the data to the main memory device 5. do. moreover,
The data at the corresponding address in the other buffer storage units f7b, 7c is invalidated.

[For production]

According to the memory control method of the present invention, whether a write address exists in a proprietary state in the buffer storage device to which writing is to be performed, or exists in a shared state among multiple buffer storage devices, or In either case, a partial write to the main memory can be converted into a full write even if it does not exist in the device.

For example, the buffer storage device 7a to which writing is to be performed
In some cases, the write address at that time does not exist, but the address exists in other buffer storage devices 7b and 7C as a write address from the corresponding processor.

In this case, the data written in the main memory device 5 is transferred to the buffer memory device, the transferred data and the data written at that time are merged, and all are written to the main memory device, and then the other buffer memory By invalidating the data at the corresponding addresses of the devices 7b and 7C, it is possible to prevent different data from existing among the plurality of buffer devices.

In other cases, partial writing can be similarly converted to full writing, and in all cases, partial writing can be converted to full writing while ensuring data consistency.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a system configuration diagram of a multiprocessor system according to the memory control method of the present invention.

The system shown in the figure includes four processors CPtJ11
a- CPUI 1 d and two main storage units (MSU
) 12a, 12b and their main storage devices 12a, 12b
It is composed of a storage control unit (MCU) 13 that controls the .

Each of the CPUs 11a to 11d is equipped with a buffer storage control section I4 (FIG. 3) that controls writing and reading to and from a buffer storage section composed of a high-speed, small-capacity memory.

FIG. 3 is a diagram showing a specific configuration of the buffer storage control section 14 described above.

Each CPU 11a-1id in this embodiment processes instructions through pipeline control. Although not shown in detail in FIG. 3, each CPU includes an IU unit 15 that controls the entire pipeline and calculates addresses for accessing the buffer storage section, and performs operations such as data addition, subtraction, multiplication, and division. An arithmetic control unit EU16 is provided.

The logical addresses from pinto 1 to pinto 31 output from IU 15 are set in register EAR17 and output to comparators 22 and 23.

Address translation buffer (TLB) 1B is B, which will be described later.
This is a memory that stores logical addresses of data registered in the SDATA section 20 and real addresses corresponding to the logical addresses. This TLB18 has IU1
Bits 13 to 19 of the logical address output from 5 are input, and the PRIMARY corresponding to that address
, ALTERNATE are read simultaneously.

The logical address output from the register EAR17 is compared with the logical address of the address translation buffer TLB 18 by the comparators 22 and 23, and the real address of the matching address is read out, and the logical address is converted from the logical address to the real address. Conversion takes place. The real address read at this time is the BSTAG section 19 and the register RAR26.
is output to.

It is composed of eight associative levels from WAYO to WAY7, and address information of the same block group on the main memory is written in the eight WAYs.

The BS TAGAlB12WAY f7) outputs are input to 2×8 comparators 21, and are compared with the real address output from the REAL section 18b of TLBI8 in the comparators 21. From the comparison results of the comparator 21 and the comparison results of the comparators 22 and 23, it can be determined whether the logical address output from the IU-15 exists in the WAY of the BS TAG AlB 12 or not.

Here, the logical address output from the IU 15 is converted into a 4-byte page address using the virtual address method, and the address data is bit 1 to bit 3.
For bits 20 to 31 of 1, the logical address and real address match.

Pinto 2 from the above BS TAGAlB12.1015
Logical addresses (-real addresses) from 0 to 25 are input, TLB 18 f7) LOGICAL section 18
a(7) Without waiting for the comparison result, the REAL section 18b and each W
It is possible to compare with the address data of AY. This speeds up the BS TAGAlB12 search.

In this embodiment, the BS TAG section I9 contains VALII (VALII) that indicates whether the entry is valid or invalid.BIT: In addition to the V flag and real address bits consisting of bits 1 to I9, A CHANGE BIT: C flag is provided to clearly indicate whether writing has been performed from the processor. This C flag is set to "1" when a processor writes, and reset to "o" when another processor writes to the same address.

BS DATA section 20 is BS TAGAlB12AY
It is a data memory having a configuration corresponding to the number of data. This B
The SDATA section 20 module outputs bits 20 to 25 of the logical address (real address) from the EAR 17 one machine cycle later than the BS TAG AlB 12, and reads out the data specified by the address.

This rewriting of data stored in the BS DATA section 20 is performed using LRU (Least Recently U
sed) method, and are evicted from the BS TAG AlB 12BS DATA section 20 in descending order of reference frequency.

The data read from the BS DATA section 20 is
The IGN & 5ELECT circuit 24 selects a desired data WAY based on the comparison result of the comparator 21, and at the same time selects from which direction of the WORD REG 25 the data is to be stored, that is, from the beginning of the WORD REG 25, or from the beginning of the WORD REG 25. It is determined whether data will be stored starting from the end.

Instruction words, operand data, etc. stored in the WORD REG 25 are output to the IU 15 and used as operand data for instruction decoding and calculations.

In TLB I8, the address data converted from the logical address to the real address (outputs B and C of TLB18)
) is set in the real address register (RAR) 26. The address data set in the RAR 26 is stored in the register 5TAR 27 in order to absorb gaps in access timing of the main storage unit (MSU) 12a or 12b.

The CPU write data is from EU16 to E-UNIT.
ALIGN circuit 28 via 5TORE DATA lotus
be taken in. The output of the ALIGN circuit 28 is BS
Register 5DR as DATA1B28 write data
29, and is also set in the store buffer (STB) 30 as write data to the main storage device.

The write address and write data set in the store address register (STAR) 27 and the store buffer (STB) 30 are outputted via the selector 31, 32 and the registers MSAR33 and MDI34 when the MCUI3 becomes able to accept the data.

Further, the register BIAR 35 is a circuit that stores a block transfer address output from the MCU 13, which will be described later, or an address to be invalidated.

A circuit having the same configuration as the buffer storage control unit 14 described above is provided in each CPU I a to lid, and the MSAR 33 and MD I of each buffer storage control unit 14
34, addresses and data are set regardless of the state of the MCU 13, and these data are output to the MCU 13 independently of pipeline processing.

Next, the circuit configuration of the MCU (memory control unit) 13 is
This will be explained using figures.

The MCU 13 is provided with four boats 41a to 41d that store access requests, corresponding to the four CPUs 11a to lid.

The access requests stored in the ports 41a to 4]d are prioritized for the right to use the pipeline by the priority circuit 42, and the request with the highest priority is sent to the timing register T1. Then, at the next timing, the main storage device (MSU) is transferred from the timing register T2.
) 12a or 12b, and is also output to the timing register T3. Timing register T3~T
7 is for timing read and write operations.

The request output from timing register T1 is
When the write request is from the CPU, it is checked by referring to the TAG sections 43a to 43d whether or not an address matching the current write address exists in another CPU. Here, the TAG units 43a to 43d are circuits that store a copy of the BS TAGAlB12 address information of the buffer storage control unit 14 described above for each CPU.

FIG. 6 shows TAG sections 43 a to 43 d of the MCU 13.
FIG. The TAG sections 43a to 43d are connected to the BS TAGAlB1 of the buffer storage control section 14 shown in FIG.
Both have similar configurations. BS TAGAlB1
The second point is that CHANGE BIT: C is not provided.

Returning to Figure 5, when there is a request from the CPU, the TA
Address information corresponding to the write address is sequentially read from the G sections 43a to 43d, and the read address is compared with the write or read address from the IU 15 by the comparators 44a to 44d. If a matching address exists, the address information is output to the corresponding registers Br45a to Br45d. The address information output from these registers B147a to 47d is
It is output to the register BIAR35 of the buffer storage control unit 14 of each CPU mentioned above.

At this time, if the request from the CPU is a write request to the buffer storage section and the same address exists in another CPU, an instruction is issued to the other CPU to invalidate the corresponding address.

Register MSRDI46 is main memory device (MStJ) 1
This is a register that stores data read from 2a and 12b. The data stored in this register MSRD 146 is stored in the SYNDROME change circuit (SYD) 4.
After the ECC code is checked at 7, register MSR
It is stored in DII48.

The data stored in register MSRDII48 is
After error correction is performed in the RRECT circuit (COR) 49, the signal is output to the target CPU via the register MSRDI[[50 and MCUDO51.

The boat DI PORT 52 is composed of four registers that store write data output from the four CPUs, and among the data stored in this DT PORT 52, the data corresponds to the boat given priority. Data is selected by knowledge 53 and stored in MSWDr 54. For the output data of MSWD I54, GEN section 5
An ECC code is created in step 5, and the data to which the ECC code is added is sent to the MSU 12a via the MSWDI 156.
Or it is output as write data to 12b.

Next, the configuration of the main storage units (MSU) 12a and 12b will be explained with reference to FIG.

The memory 61 of the MSUs 12a and 12b of this embodiment is composed of a plurality of banks that can operate simultaneously. This is 1
This is to improve main memory throughput by allowing different addresses in different banks to be accessed simultaneously, since it typically takes multiple machine cycles to perform one memory access.

For example, in the MSU shown in FIG.
By changing the lower address of the read address from the MCU 13 stored in 2 in units of 8 bytes,
Eight banks can be accessed simultaneously. The 8 x 8 = 64 hide data read from these 8 banks is held in the register DOR63 and sent to the MC.
It is output to U13.

Furthermore, in the case of writing, the data output from the MCU 13 is stored in the register DIR64, and the data is written into the bank specified by the address of the register ADR62.

Next, the contents of data read and write processing based on the memory control method according to the present invention will be explained with reference to the flowcharts of FIGS. 8 and 9.

Below, the operation of the buffer storage control unit I4 and MCUI3 of the CPU 1i'a when a read or write request is issued from the CPU 11a will be explained.

First, the operation in the case of reading will be explained with reference to the flowchart of FIG.

The buffer storage control unit 14 compares the address information of the BS TAG unit 19 and the read address output from the rU 15, and determines whether a matching address exists (FIG. 8, SL).

The same address as the read address is the BS TAG section 1
9, the buffer storage control unit 14 reads data corresponding to that address from the BS DATA unit 20 and sets it in the WORD REG 25 (S2).
, the read process ends.

If a matching address does not exist in the BS TAG section 19, the CPU 11a issues a block read request to the MCU 13 (S3).

When a block transfer request from the CPU is accepted, the MCU
13 reads the block data of the corresponding address from the MSU 12a or 12b (S4).

Furthermore, the corresponding TAG sections 43a to 43d of the MCU 13
Register the block address at this time and VAuD
BIT: Set V to "1" (S5).

In the buffer storage control unit I4, MSUI2a or 12b
The block address transferred from the BSTAG section 19
19 in total, and since data will be written to that address, VALID B of the BS TAG section 19.
Set IT to V=1 and CHANGE BIT to C=1 (S6).

Then, the data transferred as a block from the MSU 12a or 12b is bypassed and output to the IU 15 (S7).
.

Next, the operation when a write request is issued from the CPUIA will be explained with reference to the flowchart of FIG.

First, the buffer storage control section 14 controls the BS TAG section 19.
Then, it is checked whether there is an address that matches the write address from the IU 15 (FIG. 9, S8).

If a matching address exists in the BS TAG section 19, then the CHANGE BTT of the BS TAG section 19
: Determine whether C is "1" (S9).

At this time, the corresponding address exists in the BS TAG section 19 in response to the write request from the IU 15, and C=1.
If so, it indicates that the latest data has been written to the buffer storage control unit 14 of the CPU 11a.

Therefore, the data at the corresponding address of the BS DATA section 2o is read out, and the read data and write data are merged in the store buffer (STB) 30.
It is output to the MCU 13 as 8-byte data. Furthermore, the write data at this time is written to the corresponding address of the BS DATA section 2o (S9).

With this, MCUI3 can connect MS in one operation.
Data can be written to U, and a partial write can be converted into a full write.

Furthermore, if the corresponding address exists in the BS TAG section 19 in response to a write request from the IUI 5, and C=0, the BS DATA section 20 contains the MSU 12a or 12.
This means that the data read from b is stored.

In this case, first, the 746 part 43a is sent to the MCU 13.
~43d search request is output (Sll) MCU13
Then, in response to this search request, 746 parts 43a to 43d are searched from the write address at that time, and other CPs are searched.
Check whether there is an address matching U (S12
).

If an address matching any of the 746 sections 43a to 43d exists, the MCU 13 instructs the corresponding CPU to invalidate the corresponding address in its own BS TAG section 19 (S13).

Upon receiving the invalidation instruction from the MCUI 3, each CPU sets the ■ flag in the BS TAG section 19 to "0" and
Set the flag to "0" to invalidate the corresponding address.

In the determination in step 312, the 746 part 43a of the MCU 13
43d, or in step 313, the BS TAG section 19 of another CPU
After the corresponding address is invalidated, the CPU that issued the write request sets rl to the C flag of the corresponding address in its own BS TAG unit 19 (S14
).

Thereafter, in step SIO described above, the write data from the EU 16 is written to the corresponding address of the BS DATA section 20.

In the determination in step S8, if the write address output from the IU 15 does not exist in its own BS TAG unit 19, the process proceeds to step 315 and issues an exclusive block read request to the MCU 13.

In response to this block read request, the MCU 13 selects 7 addresses that match the read address at that time.
46 parts 43a to 43d (S
16).

If a matching address exists in the 746 sections 43a to 43d, the corresponding CPU is instructed to invalidate the address (
S17).

When it is determined in step S16 that there is no matching address in the 746 sections 43a to 43d, or after invalidating the corresponding address in the other CPU0BS TAG sections 19 in step S17, block transfer is performed to the MSU 12a or 12b. A request is issued (318).

Furthermore, the CPU 1la that issued the write request at this time
The block transfer address is registered in the TAG section corresponding to the block transfer address, for example, the TAG section 43a (S19).

In the buffer storage control unit 14 of the CPU 11a, the MSU1
Since the data block transferred from 2a or 12b is written, the V flag of the write address is set to "1" to make the address valid, and the C flag is set to "1" to write the data. It memorizes what was done (S20).

After that, the process proceeds to step SIO described above, and the MSU 12a
Alternatively, the data transferred from 12b is written to the corresponding address of the BS DATA section 20.

As described above, in the above embodiment, for example, the address information of the buffer storage units of a plurality of CPUs (a copy of the address information of the BS TAG unit 19) is stored in the 746 unit 43a of the MCU 13.
~43d, and when the write address is shared among multiple CPUs, the CPU that issued the write request
The corresponding address of the CPU0BS TAG section 19 other than the PU is invalidated. As a result, the latest data is always stored in each CPU0BS DATA section 20 during writing and reading.

Therefore, the CPU0BS TAG that issued the write request
When there is a write address in section 19, the BS
By writing data obtained by merging the data stored in the DATA section 20 and the write data into the main storage device, partial writing can be converted into full writing while ensuring data consistency. Also, if a write address does not exist in the BS TAG section 19, the data at that address may be transferred from the main storage device, and the transferred data and write data may be merged and written.

As shown in item 2, according to the memory control method of the present invention, partial writing can be converted into full writing in all cases while ensuring data consistency in a multiprocessor system. This makes it possible to reduce the number of accesses to the main memory and improve system efficiency.

In addition, in the above embodiment, the case where partial writing is converted to full writing in a system configured with multiple CPUs was explained, but when the system is configured with one CPU, conventional memory control methods can be used. Since it is sufficient,
In the buffer storage control unit 14 described above, a means for bypassing the circuit that implements the memory control method of the present invention is provided,
The circuit may be switched between multiple CPUs and a single CPU.

Furthermore, when transferring a block of data in the main storage device, for example, instead of setting the block data in the store buffer 5TB30 after the transfer to the BS DATA unit 20 is completed, the block data is transferred to the store buffer in parallel with the block transfer. Data can also be set in Sofa 5TB30. By setting data in the store buffer in parallel with data transfer, the time required to write data to the main memory can be further reduced.

〔Effect of the invention〕

According to the present invention, a partial write can be converted into a full write in all cases while guaranteeing data consistency between a plurality of buffer storage devices and between a buffer storage device and a main storage device. It is possible to reduce the number of accesses and further improve the processing efficiency of the system.

[Brief explanation of drawings]

1(a) and (b) are diagrams explaining the principle of the present invention, FIG. 2 is a system configuration diagram of a multiprocessor system according to an embodiment, and FIG. 3 is a circuit configuration diagram of the buffer storage control unit 14. 4 is a block diagram of the BS TAG section in FIG. 3, FIG. 5 is a circuit block diagram of the MCU, FIG. 6 is a block diagram of the TAG section of the MCU, and FIG. 7 is a block diagram of the MS TAG section.
FIG. 8 is a flowchart when reading data, and FIG. 9 is a flowchart when writing data. 5.12a, 12b--Main storage unit (MSU), 6a
~6c...Processor, 7a~7c...Buffer storage device, 11a~lid.--CPU, 13...Memory control unit (MCU), 14...Buffer storage control unit.

Claims (1)

[Scope of Claims] 1) Consisting of at least one main storage device, a plurality of processors, and a plurality of buffer storage devices corresponding to the plurality of processors, with a storage-through connection between the main storage device and the buffer storage device. In the memory control method, when a write request is issued from a processor and the write address exists in the buffer storage device of the processor in an exclusive state (1a), the corresponding address of the buffer storage device is The data written by the processor is merged with the data written by the processor, and all data is written to the main memory (1
b) When the write address exists in a shared state among multiple processors (2a), the data at the corresponding address in the buffer storage device of the processor that issued the write request and the write data are merged and stored in the main memory. All writes are performed (2b), and the data at the corresponding address in the buffer storage device of a processor other than the processor that issued the write request is invalidated (2c), and if the write address does not exist in the buffer storage device of the processor concerned, (3a) transfers the data at the corresponding address in the main memory device to the buffer storage device for writing (3b), merges the transferred data with the write data of the processor, and writes all the data to the main memory device. (3c) A memory control method characterized by invalidating data at a corresponding address in a buffer storage device of another processor (3d). 2) Consisting of at least one main storage device, a storage control device that controls writing and reading to and from the main storage device, a plurality of processors, and a plurality of buffer storage devices corresponding to the plurality of processors; In a memory control method in which data between buffer storage devices is managed in a store-through manner, a TAG that stores copy information of part or all of the address information stored in the plurality of buffer storage devices in the storage control device; When a write request is issued from a processor, the write address exists in the buffer storage device of the processor, and the same address of another processor is not registered in the TAG portion of the storage control device. The data at the corresponding address of the buffer storage device of the processor and the write data are merged and all written to the main storage device, and the write address exists in the buffer storage device of the processor and the TAG of the storage control device When the same address of another processor is registered in the TAG section, merge the data at the corresponding address in the buffer storage device of the processor with the write data, write all of it to the main memory, and write the write address in the TAG section. Instructs other processors in which the same address is registered to invalidate the data at the corresponding address in their own buffer storage device, and when the write address does not exist in the buffer storage device of the processor, Transfer the data at the corresponding address on the main storage device to the buffer storage device of the processor, merge the transferred data and write data, write all of it to the main storage device, and write the write address in the TAG section. A memory control method characterized in that an instruction is given to other processors in which the same address is registered to invalidate data at the corresponding address in the own buffer storage device. 3) Corresponds to the address registered in the buffer storage device, is set when data is written from the processor, and is reset when data is written to the same address in another buffer storage device. When a write request is issued from a processor, the write address exists in the buffer storage device of the processor, and the same address of another processor is not registered in the TAG section of the storage control device. In some cases, the data at the corresponding address in the buffer storage device of the processor and the write data are merged and all written to the main storage device, and the write address exists in the buffer storage device of the processor and the storage control device When the same address of another processor is registered in the TAG section of the processor, the data of the corresponding address in the buffer storage device of the processor and the write data are merged and all written to the main storage device, and the data is written to the TAG section of the processor. An instruction is given to other processors in which the same address as the write address is registered to invalidate the change flag and data of the corresponding address in their own buffer storage device, and the write address is registered in the buffer storage device of the processor. If the data does not exist in the main memory, the data at the corresponding address in the main memory is transferred to the buffer memory of the processor, the transferred data and write data are merged, and all are written in the main memory, and the TAG section Claim 2 characterized in that an instruction is given to another processor in which the same address as the write address is registered to invalidate the change flag and data of the corresponding address in its own buffer storage device.
Memory control method described. 4) When data at a corresponding address in the main storage device is transferred to a buffer storage device, the transfer data and write data are merged and set in the store buffer in parallel. Or the memory control method described in 3. 5) A mode selection means is provided for selecting a mode in which writing is performed with reference to the address registered in the buffer storage device and a mode in which writing is performed without reference. Or the memory control method described in 3.