JPS60202475A - Smoothing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a smoothing circuit that displays a smooth image by interpolating pattern data stored in an image memory.

[Old technical background of the invention and its problems 1 In systems that display character pattern data such as letters and figures on a display screen, such as teletext systems, captain systems, and computer systems, characters stored in VC such as character generators, etc. A code signal corresponding to the pattern is received, and character pattern data is read out and loaded into the image memory VC using this code signal.

After the character pattern data is inserted and shuffled, the character pattern data is read out from the image memory and displayed.

For example, if the original character I interface data of the characters "v", "/", and "." stored in the image memory shown in FIG. 1 are displayed on the display screen unprocessed, As shown in the figure, roughness becomes noticeable on the diagonal cliff. Here, Ls % L 14 in the figure is formed during the scanning table or field period, and the scanning line L2m shown by the solid line is formed during the even field period.

Furthermore, a block indicates a basic unit pixel, and the pattern data of the image memory in FIG.
Commonly used in 2.

Therefore, in order to make it easier to see the diagonal lines of characters that can be displayed, it has been proposed to perform smoothing processing on the original pattern data before displaying it. The thorax is added.

Therefore, when compared with FIG. 2, it is generally smoother and easier to see. However, [2, when the slope part is steep as shown in Figure 3+aJ, half the pixels in the hatched part of pixels dx to d6 are not deleted, so the smoothness is not sufficient, and the third
There was a problem in that the non-display part as shown in the figure (cl) was filled with half the pixels d7 to dxo, and "." was displayed as ",".

] A smoothing circuit that deals with this problem and performs even smoother smoothing processing by adding or deleting small pixels with a width of 100 pixels is disclosed in Japanese Patent Laid-Open No. 58-751.
It is listed in ffd in Publication No. 92.

A display example of this second smoothing process is shown in FIG.

As is clear from the figure (al), the smoothing process is performed sufficiently smoothly in the steep 1... slope portion VC.

However, for the 45° diagonal line [/] (~, the display is stepped as shown in the same figure (bl) (lh<i12, so the display is stepped), and for 1-o'', the entire vertical length is There is a problem that the display becomes distorted.Also,
To remove a 30° or 60° diagonal line that cannot be visually smoothed to a sufficient thickness, a four-frequency display block is required compared to adding or deleting small pixels in the figure. Therefore, it also had the disadvantage of requiring a circuit configuration for high-speed processing.

As mentioned above, in conventional smoothing circuits, the smoothing process is not performed only on the shaded areas, but on all the sloped areas, so there are cases where it becomes impossible to identify the original character pattern. There were problems with visual performance, such as the display being distorted or not being displayed at the required thickness.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a smoothing circuit that displays a hatched portion in a smooth image state and with a required overall thickness without distorting pattern data stored in a stroke memo IJK.

[Summary of the invention]

In this invention, the diagonal i\ilj group is detected by extracting data for a total of three lines, the currently displayed line and the lines above and below it, from the pattern data stored in the image memory, and the slope of the diagonally shaded portion is The above object is achieved by adding or deleting a basic unit pixel or a half pixel having a half pixel having a width of 1 of this unit pixel depending on the armpit of the unit pixel.

[Embodiments of the invention]

Embodiments of the smoothing circuit of the present invention will be described below with reference to the drawings.

First, an overview of this embodiment will be explained with reference to FIG. 5, which shows a display example when smoothing processing is performed according to this embodiment.

In these 6 actual examples, all smoothing processing is performed based on the original character pattern data shown in Figure 1 according to the degree of slant of the diagonal part. But again, 45 in the same figure (1))
Smooth display is possible even for diagonal lines. It's 1.
The sharply shaded areas in Figure 5 (al) can be displayed with sufficient thickness.Furthermore, since smoothing is applied only to the shaded areas, unnecessary smoothing is not performed as is clear from Figure 5 (cl). , the display will not be distorted, or the non-display area will not be filled up.

Next, FIGS. 6 and 7 show an algorithm for smoothing processing for adding or deleting a unit pixel or a half pixel of width i of a unit pixel during an odd field period, and the algorithm will be explained.

Here, a half pixel indicated by diagonal lines means addition, a half pixel indicated by dotted line means deleted, and "appetizer" indicates that it does not matter whether there is a unit pixel or not. In addition, FIG. 7 fal to (g+ is FIG. 6 f showing smoothing processing that operates the left half pixel) showing the smoothing process that operates the right half pixel.
Each of at to fgl has left and right line symmetry.

fat, (bl, icl &'j' in Figures 6 and '1)
Interpolation is performed for the diagonal portions with a slope of 45° downward to the left and downward to the right by adding half a pixel, and 1. The B-axis direction is added by half a pixel, and (fl, fgl are downward left and right slopes of 300 or 6
This shows smoothing processing performed by deleting half a pixel to remove a rough interval for a 0° hatched area.

Therefore, in order to determine whether to add or delete half a pixel at a certain point, the data of the currently displayed line and the data of the lines above and below it are used. Therefore, the conditions for adding or deleting the half-pixel system in the case shown in FIG. Data of the currently displayed line R: Data one line above the currently displayed line F: Data one line below the currently displayed line.The condition for adding half a pixel to a diagonal line of 11145° (the 6
Figure a, b, c) Rtn-1・Rtn-Ctn-t-Ctn-Ctn++
=1Rtn-'1 ・Rtn・Ctn-+; CLn・
ji'tn-1Rtn-1・Rtn-,1(tn-)-
1・Ctn-1・Ctnbusj,n〒1”-Pen-s
-]〒n=1 (Conditions for adding half a pixel to a diagonal line of 2160° or 30' (Fig. 6 d, e) Rtn-1・RtnφRtn+1・Ctn-1-Ct
n-Ctn-+-1-FtKore-rr+1=I Rtn-1 ball t n・ct n-+ -Ctn ・(5
'1rrh -rr1 1 @ F't n'F't
rr) Conditions for adding half a pixel to a diagonal line of I-1+3160° or 30° (Fig. 6 f, g) Rt;l ・Rtn・Rtn+1 ・Ct1 Go 1
Ctn・F"tn21 ・Ftn・F'tn+-1=1
=1.

Note that the condition of placement shown in FIG. 7 is based on the above-mentioned left-right symmetry.
1 is exchanged with each other. It's Kade.
Due to the vertical symmetry with the smoothing process in the odd field period, the conditions for the smoothing process in the even field period are the above conditions +11 to (3) for FIG.
)'s RSF"li7 are exchanged with each other, and FiR and F are exchanged with each other for FIG.
The condition is that n-1 and tn+1 are exchanged.

Here, the smoothing process for adding unit pixels by the above-mentioned addition in half-pixel units will be explained with reference to FIG. 8.

When smoothing the original character pattern data shown in Figure 8 (al), first the left half pixel is added as shown in Figure 8 (bl) as shown in Figure 6 (because the condition of dl is satisfied, as interpolation for the 30° diagonal line). Furthermore, as the interpolation for the 45° diagonal line satisfies the condition +a+ in Figure 7, the right half pixel is added as shown in Figure 8 (cl).
A unit pixel is added by adding half pixels to the left and right of the point.

According to the above conditions, smoothing processing with an inclination of 45° and 60° is performed on the original pattern data shown in FIG. And, the shaded area is displayed with sufficient thickness, and for the original pattern data shown in Figure 1 (cl), the image of "." of the data stored in the image memory as shown in Figure 5 (cl). The center of the circle on the display is not filled in, and the entire display is not distorted.

A block diagram of a smoothing circuit that performs the above-mentioned smoothing process is shown in FIG. 9, and will be explained.

The image memory 10 includes a control unit (not shown) during the non-display period.
The 8-bit parallel image data supplied from the 8-bit parallel image data, for example, the image data shown in the first section 1, is inserted. From this image memo January 0, image data is read out during the display period and subjected to smoothing processing, and then displayed as shown in FIG. 5 (not shown).

The address used when reading image data from the image memory 1() will be explained below.

Clock pulse C supplied from an oscillator etc. (not shown)
An octal bit counter 12 counts P (FIG. 10a), and a byte counter 14 counts the 8-bit unit signal output from the bit counter 12, and supplies the address of the image data in the column direction. (Figure 10b). In addition, the line counter 16 counts the signal outputted from the byte counter 14 in units of one horizontal period, and the line counter 16
The field counter 18 counts the I/O signals outputted from the signal generator 6 in units of l vertical periods. 4, the count value of the bit counter 12 is decoded by the bit decoder 19, and the address rotary nockles PLPI, PLP2, P-1 lower p (multiple H
Provide IO diagram f-h).

Here, as described above, in this embodiment, it is currently exposed. For this multiple readout, the line generation counter 20 is first loaded with the address Y-1 of the previous line supplied from the line counter 6 by the address load pulse A/fLP (FIG. 10d). By the row direction address Y-1 supplied from the line generation counter 20 to the data bus and the column direction address
, pattern data is supplied onto the data bus, and this pattern data is applied to the load pulse PLPI (flE
Fig. 10 f) is latched by the latch circuit 22 by K.

Next, the line generation counter 20 is incremented by the address clock ADCK (FIG. 10e) and supplies the address Y of the current line to the address bus. From the image memory IO, pattern data specified by the address
The voltage is latched by the latch circuit 26 by (il 10g). Exposure C, the line generation counter 20 is incremented by the address clock A D CK VC and the address of the next line Y + 1. ? feeds the address bus. Similarly, from the image memo IJIO, address X, Y
The pattern data designated by +1 is supplied, and this pattern data is loaded into the parallel-to-serial conversion circuit 30 by the load pulse P L P. Further, by this load pulse P L P, the pattern data of the previous line and the current line held in the latch circuit 22.26 are loaded into the parallel-to-serial conversion circuits 24.28, respectively. Therefore, the pattern data of a total of three lines, the previous line, the current line, and the next line, are synchronously input to the parallel-to-serial conversion circuits 24, 28, and 30 (FIG. 10 J-K).

Three lines of pattern data from the parallel-to-serial conversion circuits 24, 28, and 30 are supplied to the smoothing section 50. Here, as described above, the conditions for smoothing processing in the even field period are vertically symmetrical with those in the odd field period. Therefore, the switches 4042 are respectively switched by the field index l output from the field counter 18, and the pattern data of the previous line outputted from the parallel-to-serial conversion circuit 24 and the pattern data of the previous line outputted from the parallel-to-serial conversion circuit 30 are changed. Line pattern data is converted and smoothing s50 processing is common.

Next, the clock pulse CP (Fig. 10a) changes from "H" to "L".
A smoothing unit 50 that divides a unit pixel into two depending on the situation and adds and deletes a half-stroke or adds a unit pixel.
The details will be explained with reference to FIGS. 11 and 12.

In FIG. 11, the latch times %51-56 operate as delay circuits to delay the pattern data for three lines by one clock pulse CP, and the
Rtns, CtnSCtn-1, Ftn, F't
Supply n-1.

The detection circuit 60 also receives RtrrH, Ctrrl-ISFtrrh from the parallel-to-serial conversion circuit 24.28°30.
is supplied. These Pl, P2 span [)Pl, DP2
Output as .

Next, the i+P Nll of the upper self-detection circuit 60 is shown in FIG. 12 and will be explained.

Pattern data it, c, F manually input to the detection unit y^60
The inverter 61 converts the turn data R to ``-6''.
Pattern data E (, C5F) with polarity inverted from C and F
(The output of this inverting section 61 is supplied to the first and second detecting sections 62 and 63.

In the first detection unit 62, the signal P1 for adding the left half pixel shown in FIG. 6 (al to tel), and in the second detection unit 63, No. 16 I) PI is obtained, which performs the deletion of half a pixel.The respective outputs Pi and DPI of these detection sections 6263 are supplied to the color selection section 70. Channel 3 and fourth detection unit (not shown) for addition and deletion
A signal P2.1)P2 is also output from the color register 80, and the color sector unit 70 converts the foreground color signal A or the background color signal B supplied from the color register 80 to the signal PI.
, P2, DP11DP2. A circuit diagram of this color selection section 70 is shown in FIG. 13, and will be explained. The signals P1, P2, DPI, and DP2 are first input to the output section 72, and the signals P1 and DPI for the left half pixel and the signal P2.1 for the right half pixel are selected depending on the polarity of the tarok pulse CP. It is output as number P. The selection unit 74 selects m supplied from the color register 80 as color 100 A by using the A8P.
and background color signal B are selected and output as R, G, and B signals.

These R, G, and B signals are sent to -d byte counter 4.
A display period signal DSE is obtained by gating the horizontal display period signal HDSE from the byte decoder 90 that decodes the count value of the line counter 6 with the vertical display period signal V7SE from the line decoder 92 that decodes the count value of the line counter 6.
The signal is gated in a gate circuit 94 and supplied to a display section (not shown).

According to this embodiment configured as described above, FIG.
The pattern data (16) stored in the image memory shown in column 1 is displayed on the display section as shown in column 1fl of FIG.

As explained above, according to this embodiment, a diagonal line part is detected and a unit pixel or a half pixel is added or a half pixel is deleted depending on the degree of inclination, so that the pattern data stored in the image memory is It can be displayed smoothly without distortion and with sufficient thickness. Therefore, the effect of visually identifying pattern data is improved.

In this embodiment, the case of interlaced display is shown, but in interlaced display, the lowest viratrator of the line address may be used instead of the field index FI.

〔Effect of the invention〕

According to the present invention, as described above, the diagonal line portion is detected and smoothing processing is performed according to the degree of inclination, so that the pattern data stored in the image memory can be smoothed without distortion, and the thickness can be increased to a sufficient thickness. can be displayed in
The visual identification effect of pattern data is improved.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing pattern data, FIG. 2 is an explanatory diagram showing an example of the display in FIG. 1, FIGS. 3 and 4 are explanatory diagrams showing an example of display by a conventional smoothing circuit, and FIG. Explanatory diagram showing a display example by the smoothing circuit of the present invention, No. 6
8 to 8 are explanatory diagrams explaining the smoothing process of the smoothing circuit of the present invention, FIG. 9 is a block diagram showing an embodiment of the invention, and FIG. 1O is a time chart showing the operation of each part of FIG. 9. , FIGS. 11 to 13 are circuit diagrams showing details of each part of FIG. 10, and FIG. 14 is an explanatory diagram showing an example of display of 11 ports by the smoothing circuit of the present invention. 10,... Image memory 12.14.1 Melon 1 & 20... Counter 19.90
．． 92...2 decoders 26...Latch circuit 24.2 & 30...Parallel-to-serial converter 50...Smoothing department agent Patent attorney Kensuke Chika (and 1 other person) ) Figure 5 Figure 6 (e) (Cl) (!? (j LL Figure 14 (a) (b) Procedure Supplementary IT Yen (J) Formula) % Formula % 1. Case Display Patent Application 1982 -4) 8143 yen 2, name of the invention Smoothing circuit 3, relationship with the amendment 1 case 1! 1ii'l Junjin (307) Co., Ltd.: Nakatari 4, agent 105 Shibaura, Minato-ku, Tokyo -Ding [ ] 1 No. 1 No. 1983r June 26th (Shipping port) 6. Drawings subject to amendment

Claims (1)

[Scope of Claims] An image memory in which pattern data constituting IJ hooks is stored in the row direction and column direction by unit pixels;
A storage means for reading out and holding nine unit pixels, which are the pattern data of the currently displayed rows and the rows above and below the image memory, from the image memory; diagonal component detection means for detecting a diagonal line component from a unit pixel and eight unit pixels around it; 1. A smoothing circuit comprising: smoothing means for adding or deleting a half pixel having a value of 0 to the unit pixel being displayed.