JPS60202474A - Smoothing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a smoothing N-way for displaying a smooth image by interpolating pattern data stored in an image memory.

[Technical background of the invention and its problems]

In systems that display character pattern data such as letters and figures on a display screen, such as a teletext system, a captain system, and a combination system, a code signal corresponding to a character pattern stored in a character generator, etc. is received, and this code signal is The character pattern data is read out and written into the image memory.

After the character pattern data is written, the character pattern data is read out from the image memory and displayed.

For example, the characters rVJ, r/J, r stored in the image memory shown in FIG. If the original character pattern data of `` is displayed unprocessed on the display screen, roughness will be noticeable in the diagonal lines as shown in Figure 2.Here, L1-1 in Figure 1 .14 indicates a scanning line, the scanning line L2m-1 (m: integer) indicated by a broken line is formed during an odd field period, and the scanning line L2m indicated by a solid line is formed during an even field period. The pattern data of the image memory (the first
) is commonly used in both odd field periods and even field periods, for example, scanning lines Lj 1 + Ij2.

Therefore, in order to make the diagonal lines of the displayed character easier to see, it has been proposed to perform smoothing processing on the original pattern data before displaying it. A third element is added.

Therefore, when compared with the unprocessed FIG. 2, it is generally smoother and easier to see.

However, when the slope is steep as shown in Figure 3(a), half the pixel in the hatched area of pixels di-d6 is not deleted, resulting in insufficient smoothness. There was a problem in that the display part was filled with half the pixels d7 to d1o, and "0" was displayed as "1.".

To deal with this problem, a smoothing circuit is described in Japanese Patent Application Laid-Open No. 75192/1983 which adds or deletes small pixels with a width of 173 pixels to perform smoother storage processing. A display example of this second smoothing process is shown in FIG. As is clear from the figure (a), smoothing of the optical grooves is smoothly performed in the steep shaft portions.

However, for the 45° diagonal line "/", <, 11 <, 12 as shown in Figure (b), resulting in a stepped display.
Furthermore, for "0", there is a problem that the entire display is distorted in a vertically elongated manner, as shown in FIG.

Furthermore, to add or delete 1/3 small pixels,
Compared to adding or deleting 1/2 a small pixel, a high-frequency display clock is required, so the circuit configuration must be designed for high-speed processing.

As mentioned above, in conventional smoothing circuits, the smoothing process is not performed only on the shaded areas, but on all the sloped areas, making it impossible to identify the original character pattern or distorting it. This has had a problem in that it may be difficult to see, such as when it is displayed.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a smoothing circuit that displays pattern data stored in an image memory in a smooth image state without planning.

[Summary of the invention]

In this invention, the diagonal line portion is detected by reading data for a total of three lines, the currently displayed line and the lines above and below it, from the butter data stored in the image memory.
The above object is achieved by adding or deleting a half pixel having a width of 1/2 of the basic unit pixel depending on the degree of inclination of the hatched portion.

[Embodiments of the invention]

Embodiments of the smoothing circuit of the present invention will be described below with reference to the drawings.

First, an overview of the fifth embodiment will be explained by showing a display example when the smoothing process is performed according to the present embodiment in FIG.

In this embodiment, since smoothing processing is performed according to the degree of inclination of the diagonal line portion from the original character pattern data shown in FIG. Smooth display is possible even for the 45° diagonal line in (b). In addition, since the smoothing process is performed only on the shaded area, unnecessary smoothing is not performed as is clear from the figure (c), and φ
It will not be displayed with the hidden part filled in.

Next, FIGS. 6 and 7 show an algorithm for smoothing processing that adds or deletes half a pixel with a width of 1/2 of a unit pixel during an odd field period.

and explain it. Here, the half pixel indicated by diagonal lines:,
1 means that the half pixel shown by the dotted line is added, and the half pixel shown by the dotted line is deleted, and the r-tree J shows that it does not matter whether there is a unit pixel or not. Note that FIGS. 7(a) to (e) showing smoothing processing for operating half pixels on the right side are different from those in FIGS. 6(a) to (e) showing smoothing processing for operating half pixels on left side, respectively. It is line symmetrical.

In (a), (b), and (c) of Figures 6 and 7, interpolation is performed for the diagonal areas with a 45° slope downward to the left and downward to the right by adding half a pixel. )
Similarly, the smoothing processing is performed by deleting half a pixel to interpolate a diagonally shaded portion having an inclination of 30° or 60° downward to the left or downward to the right.

Therefore, in order to determine whether to add or delete half a pixel at a certain point, the data of the currently displayed line and the data of the lines above and below it are used. Therefore, the conditions for adding or deleting a half pixel in the case shown in Figure 6 are as shown in (a) representatively. Time C: Data of the currently displayed line R: Data one line above the currently displayed line F: Data one line below the currently displayed line. (1) Conditions for adding half a pixel (1st Figure 6 a, b, c) Rt
n-10Rtn'l'jtn+t@ct1-t'(4訃(41-+-+・Fll-1・Fall-1) (2) Condition for deleting half a pixel (Fig. 6 d, e) Rtn-
1'Rtn"Rtn+1°Ctn-1'Ctn@Ftn
-1@Ftn"IRtn-i°Rtn@Rtn-H"
Ctn-1''Cjfi@CjnH°Ftn-i=i.

Note that each condition in the case shown in FIG. For Figure 6, the above conditions +
+1, the condition is that R9F in (2) is exchanged with each other, and for FIG. 7, R and F are exchanged with each other, and the subscript t. -1+tn+1 are exchanged with each other.

According to the above conditions, for the original pattern data shown in FIGS. 1(a) and (b), the slope is 45° and 6c) is 0.
’05 (a)
, the display becomes sufficiently smooth as shown in (b), and the first
For the original pattern data shown in Figure (c), Figure 5 (
As shown in C), the center of the circle on the image display of the data "0" stored in the image memory is not filled in, and the entire display is not distorted.

A block diagram of a smoothing circuit that performs the above-mentioned smoothing process is shown in FIG. 8, and will be explained.

First, the control unit 10 writes image data to be displayed into the image memory 12 during a non-display period. At this time, the image data is written to the image memory 12 by DBUS via the data buffer 14, and the address to be omitted is specified to the image memory 12 by A and B IJS via the address switching unit 16. be done. The same applies when the control section 10 reads image data from the image memory 12, and designation of writing and reading is performed by the signal W/R from the control section 10. These data buffer 14 and address switching section 16 are provided to prevent a collision between the image data read from the image memory 12 during the display period and the image data accessed by the above-mentioned control section 10.

Next, smoothing processing of the image data read out from the image memo IJ12 in the display intercostals will be described.

The timing generator 20 uses the reference clock CK (FIG. 9a) supplied from the oscillator 18 to control the address switching unit 1.
An access address is supplied to the image memory 12 via 6. At this time, the address switching section 16 is controlled by a switching signal from the timing generating section 20 described above. Na4-? In this embodiment, the pattern data is stored in the I[III image memo 1J12 as 8-pit parallel. Therefore, the period for displaying one line of the pattern data is based on the pattern clock PCK (the clock CK divided by 8). This corresponds to one cycle in Figure 9 b).

As described above, in this embodiment, a total of three lines of pattern data, that is, the currently displayed line and the lines above and below it, are required, so three lines of pattern data are multiplex read out from the image memory 12. In other words, the timing generator 20 time-divisionally outputs the read addresses and load pulses RLD, CLD, FLD (see Figure 9) for three lines, so that the pattern data for three lines is output in parallel, each consisting of an 8-pit shift register. Direct conversion section 2
2, 24.

26. Here, in order to correct a timing shift of two clocks CK when three lines of pattern data are read into the parallel-to-serial converters 22, 24, and 26, the parallel-to-serial converter 24 has a 2-bit shift register 28. but,
A 4-bit shift register 3 ( ) is connected to the parallel-to-serial converter 26 .

Pattern data Rtn+11ctn+t+"Ln+1 from the parallel-to-serial converter 22 and shift register 28.30 and pattern data Rtn+Rtn-1+ from shift registers 32 to 42 as delay circuits for l clocks CK.
The unit pixel is divided into two depending on whether Ctn+Ctn-19 a) is H'' or 1L'', and half pixels are added and deleted.

That is, when the clock CK is 1H'', the left half pixel shown in Figure 6 is added or deleted, and when it is ``L'', the right half pixel shown in Figure 7 is added or deleted. recognizes whether the currently displayed line is an even field or an odd field based on the field index FI from the timing generator 20, and displays the corresponding field.
-Perform the ging process.

The pattern data smoothed by the smoothing section 50 is supplied to an AND gate 60, and unnecessary portions are masked by a display gate that is output from the timing generation section 20 and indicates the display period on the screen. ) is output.

Next, the details of the smoothing section 50 will be explained with reference to FIG. 10.

Pattern data R, C, input to the smoothing section 50
F,! :The field index F'l is supplied to the field conversion section 51. In this field converter 51, the field index FI
The pattern data R and F are exchanged by this. Pattern data R which is the output of this field converter 51
, C, F are converted into the pattern data R by the inverting unit 52.
,C.

Pattern data R, C, and FK with polarity inverted from F are converted. The output of this inverting section 52 is supplied to first and second detecting sections 53 and 54 illustrated as PLA (Programmable Logic Array). The first detection section 53 performs the addition and deletion of the left half pixel shown in FIG. 6, and the second detection section 54 performs the addition and deletion of the right half pixel shown in FIG. The outputs of these detection units 53 and 54 are output to an output unit 55.
, it is selected by the clock CK and supplied to the AND gate 60. Therefore, the clock C shown in FIG. 9a
When K is "tlH", the left half pixel is added or deleted, and when K is "'L", the right half pixel is added or deleted.

As explained above, according to this embodiment, the diagonal line area is detected and half a pixel is added or deleted depending on the degree of inclination, so that the pattern data stored in the image memory can be displayed smoothly without distortion. I can do that. Therefore, the effect of visually identifying pattern data is improved.

In this embodiment, the case of interlace display is shown, but in non-interlace display, the lowest pit of the line address may be used instead of the field index FT.

〔Effect of the invention〕

According to the present invention, as described above, the shaded portion is detected.

In addition, since smoothing processing is performed according to the degree of inclination, the pattern data stored in the image memory can be displayed smoothly without distortion, and the effect of visually identifying pattern data is improved.

[Brief Description of the Drawings] Figure 1 is an explanatory diagram showing pattern data, Figure 2 is an explanatory diagram showing a display example of Figure 1, and Figures 3 and 4 are display examples using a conventional smoothing circuit. An explanatory diagram, FIG. 5 is an explanatory diagram showing an example of display by the smoothing circuit of the present invention, and FIG.
7 and 7 are explanatory diagrams explaining the smoothing process of the smoothing circuit of the present invention, and FIG. 8 is a block diagram showing an embodiment of the smoothing circuit of the present invention. The waveform diagram shown in FIG. 1O is a circuit diagram showing details of a part of FIG. 8. 12...1iTii image memory 20...timing generation unit 22.24.26...parallel-to-serial conversion units 32-42...shift register 50...smoothing unit 53...first detection unit 54 ...Second Detection Department Representative Patent Attorney Noriyuki Chika (1 person) Engraving of drawings (no changes in content) Figure 3 Figure s4 (a) (a) Figure 5 (a) (b) ) (b) (1)) (C) Supplementary Procedures I Name of smoothing circuit 3, relationship with the case of the person making the amendment Patent n applicant (307) Stock trial Toshiba 4, agent 〒10;) Tokyo Minato 1 Meshibaura-cho "11 No. 1S" 5, date of amendment order June 268, 1981 (ITI sent for ¥7) 6, Drawing 7 subject to amendment, Contents of amendment Figures 3 and 4 of the drawings are corrected as shown in the attached sheet.

Claims (1)

[Scope of Claims] An image memory in which pattern data constituting a matrix in the row and column directions by unit pixels is stored, and pattern data for the currently displayed row and the rows above and below it from the image memory, and storage means for reading out and retaining nine unit pixels that are pattern data of the currently displayed column and the columns before and after it, and the currently displayed unit pixel and eight units around it held by this storage means. Diagonal line component detection means for detecting diagonal line components from pixels. and smoothing means for adding or deleting a half pixel having a width of 1/2 of the unit pixel to or from the displayed unit pixel according to the slope of the diagonal component detected by the diagonal component detection means. Features a smoothing circuit.