JPS60196961A - Manufacture of hybrid integrated circuit device - Google Patents

Manufacture of hybrid integrated circuit device

Info

Publication number
JPS60196961A
JPS60196961A JP59053701A JP5370184A JPS60196961A JP S60196961 A JPS60196961 A JP S60196961A JP 59053701 A JP59053701 A JP 59053701A JP 5370184 A JP5370184 A JP 5370184A JP S60196961 A JPS60196961 A JP S60196961A
Authority
JP
Japan
Prior art keywords
circuit substrate
film circuit
film
pellet
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59053701A
Other languages
Japanese (ja)
Inventor
Kenji Furuya
賢二 古屋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59053701A priority Critical patent/JPS60196961A/en
Publication of JPS60196961A publication Critical patent/JPS60196961A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

PURPOSE:To improve reliability by bonding a semiconductor pellet onto a film circuit substrate, connecting the pellet to a conductor on the film circuit substrate through wire-bonding and forming a protective coating on the pellet and the conductor by phenol resin and a film by silicone group resin. CONSTITUTION:A semiconductor pellet 2 is bonded with a predetermined section on a film circuit substrate 1 with adhesives 3, the semiconductor pellet and a conductor 4 on the film circuit substrate are connected by lead wires 5 through wire-bonding, the semiconductor pellet is protective-coated with phenol resin 6, and a film 7 is formed on the protective coating by silicone group resin. A capacitor 8 is soldered and connected to a prescribed section on the film circuit substrate by using flux 10, the film circuit substrate is dipped into an organic solvent, flux is washed and removed, and the film circuit substrate is dried. There is no possibility of the breaking of the lead wires because phenol resin is used as a protective coating agent, flux does not infiltrate owing to the silicone group resin film, and the stable quality of commodities is enabled.

Description

【発明の詳細な説明】 不発明は混成集積回路装置の製造方法、特に信頼性に優
れた膜回路基板の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a hybrid integrated circuit device, particularly a method of manufacturing a highly reliable membrane circuit board.

従来、混成集積回路装置の製造方法として、膜回路基板
上の所定部分に半導体ベレットを接着剤にて接着し、続
いてワイヤ・ボンディングにより上記ベレットと前記膜
回路基板上の導体とを接続し、続いて上記ベレットを樹
脂保護コートし、続いてコンデンサ等の受動部品、樹脂
封止されたトランジスタ、ダイオード等の能動部品およ
び外部端子を７ラツクスを使用してはんだ接続し、さら
に゛上記７ラツクスを有機溶剤にて洗浄、除去した後に
、樹脂封止する方法が一般に広く知られている・ しかしながら、半纏体ベレットの保護コート剤としては
、シリコーン系樹脂が一般的であるが、シリコーン系ｍ
脂は７ラツクス洗浄に使用する有機溶剤により膨潤し、
保護コートしたボンディング・ワイヤが切断される恐れ
がある。さらに、シリコーン系樹脂は、硬度が低いため
、製造工程中でのハンドリングの際に、保護コート部に
触れると、樹脂が変形し、同じくボンティング・ワイヤ
が切断される欠点がある。このため、保護コート済とし
て硬度の高ｉ７エノール樹脂を使用するのが好ま、しい
が、フェノール樹脂は多孔質のため。Conventionally, as a method for manufacturing a hybrid integrated circuit device, a semiconductor pellet is bonded to a predetermined portion of a membrane circuit board using an adhesive, and then the pellet and a conductor on the membrane circuit board are connected by wire bonding. Next, the above-mentioned pellet is coated with a protective resin, and then passive components such as capacitors, active components such as resin-sealed transistors and diodes, and external terminals are soldered using 7 lux. A generally well-known method is to seal with resin after washing and removing with an organic solvent.However, silicone resin is commonly used as a protective coating agent for semi-integrated pellets;
The fat swells with the organic solvent used for 7lux cleaning,
Protective coated bonding wires may be cut. Furthermore, since silicone resin has low hardness, if it touches the protective coating during handling during the manufacturing process, the resin deforms and the bonding wire can also be cut. For this reason, it is preferable to use a high hardness i7 enol resin that has been coated with a protective coating, but the phenol resin is porous.

部品をはんだ接続する工程および７ラツクス洗浄する工
程において、７ラツクス中の塩素成分が保護コート内に
浸透し、半導体ベレット表面のアルミニウム配塚に溶解
する恐れがあるという欠点がある。During the process of soldering the components and the 7Lux cleaning process, there is the disadvantage that the chlorine components in the 7LX can penetrate into the protective coat and dissolve into the aluminum mounds on the surface of the semiconductor pellet.

不発明の目的は、上記の欠点全除去した混成集積回路装
置ｖ−暢造方法を提供することにある。SUMMARY OF THE INVENTION An object of the invention is to provide a method for manufacturing a hybrid integrated circuit device that completely eliminates the above-mentioned drawbacks.

本発明の特徴は、膜回路基板上に半導体ベレットを装着
済にて接着する工程と、ベレツトをワイヤ・ボンディン
グにより膜回路基板上の導体と接続する工程と、フェノ
ール樹脂にてベレッ［ｉ−保護コートする工程と、シリ
コーン系樹脂にて保護コート上に被膜全作る工程とを少
なくとも有する混成集＋１を回路装置の製造方法にある
。The features of the present invention include a step of adhering a mounted semiconductor pellet onto a membrane circuit board, a step of connecting the pellet to a conductor on the membrane circuit board by wire bonding, and a step of bonding the semiconductor pellet to a conductor on the membrane circuit board using phenolic resin. A method of manufacturing a circuit device includes a hybrid assembly +1 which includes at least a step of coating and a step of forming a complete film on the protective coat with a silicone resin.

以下、不発明を実施例に基づいて詳細に説明する。第１
図（ａ）乃至第１図ｔｃ＋は、不発明による混成集積回
路装置の製造工程における断面図である。Hereinafter, the invention will be explained in detail based on examples. 1st
Figures (a) to 1c+ are cross-sectional views in the manufacturing process of a hybrid integrated circuit device according to the invention.

膜回路基板１上の所定部分に半導体ベレット２を装着済
３にて接着し、続いてワイヤ・ボンディングにより半導
体ペレットと膜回路基板上の導体４とｉ　ＩＪ−ド線５
で接続し、続いてフェノール樹脂６により半導体ベレッ
トを保護コートし、さらに保護コート上にシリコーン系
樹脂にて被膜７を作る（第１図（ａ）　）　、続いて、
膜回路基板上の所定部分にコンデンサ８を７ラツクス１
０を使用して、はんだ接続する（第１図（ｂ））。さら
に、膜回路基板を有機溶剤中に′浸漬し、スラックスを
洗浄、除去した後、ｉ＝膜回路基板乾燥する（第１図（
Ｃ）　）。The semiconductor pellet 2 is bonded to a predetermined portion on the membrane circuit board 1 using the attached wire 3, and then the semiconductor pellet and the conductor 4 on the membrane circuit board are bonded to the IJ-coupled wire 5 by wire bonding.
Then, the semiconductor pellet is protectively coated with a phenolic resin 6, and a coating 7 is formed on the protective coat with a silicone resin (Fig. 1(a)).
A capacitor 8 is placed at a predetermined portion on the membrane circuit board by 7 lux 1.
0 to make a solder connection (Fig. 1(b)). Furthermore, the membrane circuit board is immersed in an organic solvent, the slack is washed and removed, and then the membrane circuit board is dried (see Figure 1).
C) ).

以上、実施例で説明したように、本発明の方法によれば
、半導体ペレットの保護コート済として硬度の高いフェ
ノール樹Ｂ′＃に使用しているため、保護コート中のリ
ード線の切断の恐れはなくなる。As explained above in the examples, according to the method of the present invention, since the phenolic resin B'# with high hardness is used as a protective coat for semiconductor pellets, there is a risk of breakage of the lead wires in the protective coat. will disappear.

まｆｃ％保護コート表面にシリコーン系樹脂被膜全形成
するため、多孔質なフェノール樹脂中への７ラツクスの
浸透はなくなり、スラックス中の塩素成分による半導体
ペレット表面のアルミニウム配線の溶解の恐れも皆無と
なり、安定した商品質な混成集積回路装置の製造が可能
となった。Since a silicone resin film is completely formed on the surface of the protective coating, there is no possibility of 7lux penetrating into the porous phenolic resin, and there is no fear of the aluminum wiring on the surface of the semiconductor pellet being dissolved by the chlorine component in the slack. It has become possible to manufacture hybrid integrated circuit devices with stable product quality.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）〜（Ｃ）は不発明の詳細な説明するための
混成集積回路装置の製造工程の断面図である。 尚、図において、 １・・・・・・膜回路基板、２・・・・・・半導体ペレ
ット、３・・・・・・装着済、４・・・・・・導体、５
・・・・・・リード線に６・・・・・・フェノール樹脂
、７・・・・・・シリコーン系４１）１１１ｈ　８・・
・・・・コンデンサ、９・・・・・・はんだ、１０・・
・・・・７ラツクス。 第１図FIGS. 1A to 1C are cross-sectional views of the manufacturing process of a hybrid integrated circuit device for explaining the invention in detail. In the figure, 1...Membrane circuit board, 2...Semiconductor pellet, 3...Mounted, 4...Conductor, 5
......Lead wire 6...Phenol resin, 7...Silicone type 41) 111h 8...
...Capacitor, 9...Solder, 10...
...7 lux. Figure 1

Claims (1)

【特許請求の範囲】[Claims] 膜回路基板上に半導本ベレット全接着剤にて接着する工
程と、該ベレットをワイヤボンディングによす該膜回路
基板上の導体と接続する工程と、フェノール樹脂を使用
して該ベレットを保護コートする工程と、シリコーン系
樹脂にて該保護コート上に積換を作る工程とを少なくと
も有することを％徴とする混成集積回路装置の製造方法
。A step of bonding a semiconductor bullet onto a membrane circuit board using a full adhesive, a step of connecting the bullet to a conductor on the membrane circuit board by wire bonding, and a step of protecting the bullet using a phenolic resin. 1. A method for manufacturing a hybrid integrated circuit device, comprising at least the steps of coating, and creating a transfer layer on the protective coat with a silicone resin.
JP59053701A 1984-03-21 1984-03-21 Manufacture of hybrid integrated circuit device Pending JPS60196961A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59053701A JPS60196961A (en) 1984-03-21 1984-03-21 Manufacture of hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59053701A JPS60196961A (en) 1984-03-21 1984-03-21 Manufacture of hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS60196961A true JPS60196961A (en) 1985-10-05

Family

ID=12950122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59053701A Pending JPS60196961A (en) 1984-03-21 1984-03-21 Manufacture of hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS60196961A (en)

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