JPS60195952A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60195952A JPS60195952A JP59050949A JP5094984A JPS60195952A JP S60195952 A JPS60195952 A JP S60195952A JP 59050949 A JP59050949 A JP 59050949A JP 5094984 A JP5094984 A JP 5094984A JP S60195952 A JPS60195952 A JP S60195952A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor device
- package
- cobalt
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、半導体装置の電極形成に適用して有効な技術
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is effective when applied to the formation of electrodes in semiconductor devices.
電子機器の小屋化の傾向に伴ない、高密度実装に適した
り一ドレスタイプのいわゆるチップキャリア型半導体装
置の需要が、今後一段と増加していくものと考えら終る
。With the trend of electronic equipment becoming more compact, it is believed that the demand for so-called chip carrier type semiconductor devices suitable for high-density packaging and one-dress type will further increase in the future.
セラミックパッケージからなるチップキャリア型半導体
装置は、パッケージ基板のキャビティ底部に金−シリコ
ン共晶等でベレットを取り付け、該ペレットのポンディ
フグパッドとパッケージの内部電極とを金等のワイヤー
を用いて電気的接続を行なった後、該パッケージ基板と
キャップとを銀ろ５材を用い【接着することにより、内
部を気密封止して形成することができるものである。In a chip carrier type semiconductor device consisting of a ceramic package, a pellet is attached to the bottom of the cavity of the package substrate using gold-silicon eutectic or the like, and an electric wire is used to connect the pad of the pellet to the internal electrode of the package. After making the physical connection, the package substrate and the cap are bonded together using a silver foil material, thereby making it possible to form an airtight seal inside the package.
また、前記半導体装置の外部電極は、牛田付実装を行な
えるように、パッケージ上面に直接被着されているいわ
、ゆる印刷導体（メタライズ）層上（第１層としてニッ
ケルを、第２層として金を、めっき等の方法で被着して
形成することができる（特開昭５：ａ−３６４６８号公
報）。In addition, the external electrodes of the semiconductor device are placed on a so-called printed conductor (metallized) layer (nickel is used as the first layer and nickel is used as the second layer) that is directly adhered to the top surface of the package so that the semiconductor device can be mounted with a solid surface. It can be formed by depositing gold by a method such as plating (Japanese Unexamined Patent Publication No. 5:A-36468).
ところで、前記の如き半導体装置では、融点の低い銀ろ
う材を用いているのでパッケージを比較的低温で行なう
ことができるという利点がある反面、ろう材が金、＃！
を主成分としているため非常に高価にならざるを得ない
という欠点がある。By the way, in the above-mentioned semiconductor device, since a silver brazing filler metal with a low melting point is used, there is an advantage that packaging can be done at a relatively low temperature, but on the other hand, if the brazing filler metal is gold, #!
It has the disadvantage that it is very expensive because it contains as its main ingredient.
そこで、パッケージの封止剤として安価な低融点ガラス
を用いることにより、チップキャリア型パッケージから
なる半導体装置のコスト低減を図ることが考えられる。Therefore, it is conceivable to reduce the cost of a semiconductor device made of a chip carrier type package by using an inexpensive low-melting glass as a package sealant.
しかし、低融点ガラスを用いてパッケージを気密封止す
るため罠は、パッケージ基板とキャップとの間に低融点
ガラスを介在させた状態で、一定時間高温、たとえば４
５０℃に加熱処理をする必要がある。However, since the package is hermetically sealed using low-melting point glass, the trap requires high-temperature heating for a certain period of time, e.g.
It is necessary to perform heat treatment to 50°C.
ところが、前記のような加熱処理を行なう場合は、パッ
ケージの前記ニッケルおよび金の２層からなる外部電極
は、特に金属が薄（形成されている場合は、半田付性が
低下するため、半導体装置を半田を用いて実装すること
ができなくなるという問題が本発明者により見い出され
た。これは、金層が薄いため該金層を通して内側のニッ
ケルが酸化されること、またはニッケルと金との合金化
が進み表面に達したニッケルが酸化されることが主な原
因であると考えられる。However, when performing the heat treatment as described above, the external electrode of the package consisting of the two layers of nickel and gold has a particularly thin layer of metal (if the metal is formed thin), the solderability decreases, and the semiconductor device The inventor discovered a problem in that the gold layer cannot be mounted using solder.This is because the gold layer is thin and the inner nickel is oxidized through the gold layer, or the nickel and gold alloy The main cause is thought to be that nickel reaches the surface and is oxidized.
従って、前記問題は表面金層を厚く形成することにより
解決できるものであるが、金層な厚くするということは
、必然的に半導体装置のコスト上昇という問題を招来す
ることＫなる。Therefore, although the above problem can be solved by forming a thick gold layer on the surface, increasing the thickness of the gold layer inevitably brings about the problem of increased cost of the semiconductor device.
本発明の目的は、セラミックパッケージからなるチップ
キャリア型半導体装置の信頼性向上に適用して有効な技
術を提供することにある。An object of the present invention is to provide an effective technique that can be applied to improve the reliability of a chip carrier type semiconductor device made of a ceramic package.
本発明の他の目的は、信頼性の高い前記半導体装置の電
極形成に適用して有効な技術を提供することにある。Another object of the present invention is to provide an effective technique that can be applied to the highly reliable electrode formation of the semiconductor device.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、メタライズ層上に第１層としてコバルトまた
はコバルトを主成分とする合金を被着し、第２層として
貴金属を被着して半導体装置の電極を形成することＫよ
り、該半導体装置をパッケージのガラス封止温度に加熱
処理を行なっても、第１層と第２層との金属間の反応が
抑制されるために前記２層構造を保持することができる
ことより、該電極の酸化等による半田付性の低下を防止
でき、ひいては前記目的を達成するものである。That is, by depositing cobalt or an alloy mainly composed of cobalt as a first layer on a metallized layer and depositing a noble metal as a second layer to form electrodes of a semiconductor device, the semiconductor device is packaged. Even if heat treatment is performed to a glass sealing temperature of This makes it possible to prevent deterioration in solderability, thereby achieving the above object.
〔実施例１〕
図は、本発明による実施例１であるチップキャリア型半
導体装置を、そのほぼ中心を通る面における断面図で示
したものである。[Embodiment 1] The figure shows a chip carrier type semiconductor device according to Embodiment 1 of the present invention in a cross-sectional view taken along a plane passing approximately through the center thereof.
本実施例１０半導体装置は、セラミックからなるパッケ
ージ基板１のキャビティ２の底部にペレット３を金−シ
リコン共晶等のろう材４で取り付け、該ペレットのポン
ディングパッド５と内部電極６とを金等のワイヤ７で電
気的に接続した後、パッケージ基板封止部にセラミック
製キ゛ヤップ８を低融点ガラス９を介して接着してキャ
ビティ２を気密封止することにより、完成されてなるも
のである。In the present embodiment 10 semiconductor device, a pellet 3 is attached to the bottom of a cavity 2 of a package substrate 1 made of ceramic using a brazing material 4 such as gold-silicon eutectic, and a bonding pad 5 of the pellet and an internal electrode 6 are connected with gold. After electrical connection is made with wires 7 such as the above, a ceramic cap 8 is bonded to the package substrate sealing portion via a low melting point glass 9, and the cavity 2 is hermetically sealed. .
なお、本実施例１０半導体装置の特徴は、パッケージ基
板１′の表面に（一部は該基板１に埋設されている）タ
ングステン等の高融点金属を被着して形成されているメ
タライズ層１０の上面に、第１層１１としてコバルトな
被着し、該コバルト上面に第２層１２として金を被着す
ることにより、２層からなる内部電極６および外部電極
１３を形成したことにある。The semiconductor device of this embodiment 10 is characterized by a metallized layer 10 formed by depositing a high melting point metal such as tungsten on the surface of the package substrate 1' (a part of which is buried in the substrate 1). By depositing cobalt as a first layer 11 on the upper surface of the electrode and depositing gold as a second layer 12 on the upper surface of the cobalt, the internal electrode 6 and the external electrode 13 consisting of two layers are formed.
すなわち、前記２層構造の電極とすることＫより、低融
点ガラスの軟化温度、たとえば４５０℃まで加熱して、
パッケージの気密封止を行なうことにより半導体装置を
形成した場合であっても、該半導体装置の外部電極は極
めて半田付性が良く、容易に半田付実装を行なうことが
できるものである。これは、４５０℃の高温においても
、前記電極材料であるコバルトと金とは反応性が乏しい
ために、はとんど金属間化合物等の合金を形成すること
なく、電極形成初期の２層構造を保持していることによ
ると考えられる。That is, from the above-mentioned two-layered electrode structure, heating to the softening temperature of low melting point glass, for example 450°C,
Even when a semiconductor device is formed by hermetically sealing a package, the external electrodes of the semiconductor device have extremely good solderability and can be easily mounted by soldering. Even at a high temperature of 450°C, cobalt and gold, which are the electrode materials, have poor reactivity, so the two-layer structure at the initial stage of electrode formation is achieved without forming an alloy such as an intermetallic compound. This is thought to be due to the fact that the
なお、本実施例１の半導体装置の電極は、通常の方法で
製造されたパッケージ基板１のメタライズ層１０に、た
とえば電気めっき法又は無電解めっき法でコバルトおよ
び金を順次被着することにより容易に形成することがで
きるものである。The electrodes of the semiconductor device of Example 1 can be easily formed by sequentially depositing cobalt and gold, for example, by electroplating or electroless plating, on the metallized layer 10 of the package substrate 1 manufactured by a conventional method. It can be formed into
〔実施例２〕
本発明による実施例２である半導体装置は、前記実施例
１０半導体装置とほぼ同一のもので、電極のみ異なるも
のである。[Example 2] A semiconductor device according to Example 2 of the present invention is almost the same as the semiconductor device of Example 10, except for the electrodes.
すなわち、本実施例２の半導体装置は、電極の第１層１
１を銅、第２層１２を銀で形成したものである。That is, in the semiconductor device of Example 2, the first layer 1 of the electrode
1 is made of copper, and the second layer 12 is made of silver.
このように、第２層を銀で形成した場合であっても、前
記実施例１とはぼ同様の効果を得られ、また、はぼ同様
な方法で形成することができるものである。In this way, even when the second layer is formed of silver, almost the same effect as in Example 1 can be obtained, and it can be formed by the same method.
前記の如く電極を銅と銀との２層構造とすることにより
、該電極を備えたパッケージ基板を用いて、ガラス封止
をして半導体装置を完成せしめた場合は、ガラス封止温
度である約４５０℃において、銅と銀との界面のみに化
学的に安定な合金層が形成されるものと考えられ、それ
故全体にわたる合金が形成されにくいので、電極表面が
酸化されることによる半田付性の低下を防止できるもの
と考えられる。If the electrode has a two-layer structure of copper and silver as described above, and a package substrate equipped with the electrode is used to complete a semiconductor device by glass sealing, the temperature is at the glass sealing temperature. At approximately 450°C, it is thought that a chemically stable alloy layer is formed only at the interface between copper and silver, and therefore it is difficult to form an alloy over the entire surface, so soldering occurs due to oxidation of the electrode surface. It is thought that this can prevent a decline in sexual performance.
（１） セラミックパッケージからなるチップキャリア
屋半導体装置において、電極部をパンケージ上面に被着
形成されているメタライズ層上に、第１層としてコバル
ト、銅またはそれぞれを主成分とする合金な被着し、第
２層として貴金属を被着して形成することにより、前記
金属と貴金属とは、高温度においても合金が形成されに
くいので、パッケージを低融点ガラスで気密封止するた
めに、該パッケージを加熱処理しても、はぼ前記２層構
造を保持した電極を備えた半導体装置を提供することが
できる。(1) In a chip carrier semiconductor device consisting of a ceramic package, the electrode portion is coated with cobalt, copper, or an alloy containing each as a main component on the metallized layer formed on the top surface of the package as a first layer. By depositing and forming a noble metal as the second layer, the metal and the noble metal are unlikely to form an alloy even at high temperatures. It is possible to provide a semiconductor device including an electrode that maintains the two-layer structure even after heat treatment.
（２）前記（１）により、酸化を受けにくい電極を形成
することができるので、半田付実装が確実に行なうこと
が可能な半導体装置を提供するととができる。(2) According to (1) above, it is possible to form an electrode that is less susceptible to oxidation, so it is possible to provide a semiconductor device that can be reliably mounted by soldering.
（３）コバルトまたはコバルトを主成分とする合金と金
とは合金形成されにくいので、貴金属からなる第２層を
薄く形成することができる。(3) Since cobalt or an alloy containing cobalt as a main component and gold are unlikely to form an alloy, the second layer made of the noble metal can be formed thinly.
（４） 前記（２）および（３）より、信頼性の高い半
導体装置を安価に提供することができる。(4) From (2) and (3) above, a highly reliable semiconductor device can be provided at low cost.
（５） 第１層を銅、第２層を銀で形成することにより
、信頼性の高い半導体装置をさらに安価に提供できる。(5) By forming the first layer of copper and the second layer of silver, a highly reliable semiconductor device can be provided at a lower cost.
（６）第２層の貴金属として金を用いることにより、極
めて高い信頼性を備えた半導体装置を提供できる。(6) By using gold as the noble metal of the second layer, a semiconductor device with extremely high reliability can be provided.
（７）第２層の貴金属として銀を用いることにより、信
頼性の高い半導体装置を安価に提供できる。(7) By using silver as the noble metal in the second layer, a highly reliable semiconductor device can be provided at low cost.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもないＯ
たとえば、電極の第１層としてはコバＡ／）と銅とにつ
いて説明したが、これに限るものでなく、それぞれの性
質が発現するコバルトまたは銅を主成分とする谷金であ
ってもよいことは言うまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. For example, although the first layer of the electrode is made of cobalt (A/) and copper, the present invention is not limited to this. Needless to say, it's a good thing.
また、第２層の貴金属も実施例に示したものに限るもの
でなく、たとえばパラジウム等の貴金属であってもよい
。Further, the noble metal of the second layer is not limited to those shown in the embodiments, and may be a noble metal such as palladium.
なお、前記実施例では、内部電極と外部電極の両電極に
本発明を適用した。ものについて示したが、内部電極に
ついては、ワイヤボンディング示可能な電極であれば他
の材料または構造で形成したものであってもよい。In addition, in the said Example, this invention was applied to both an internal electrode and an external electrode. However, the internal electrodes may be formed of other materials or structures as long as they are electrodes that can be wire bonded.
図は、本発明による実施例１である半導体装置を示す断
面図である。
１・・・パッケージ基板、２・・・キャピテイ、３・・
・ベレット、４・・・ろう材、５・・・ポンディングパ
ッド、６・・・内部電極、７・・・ワイヤ、８・・・キ
ャップ、９・・・低融点ガラス、１０・・・メタライズ
層、１１・・・第１層、１２・・・第２層、１３・・・
外部電極。
代理人 弁理士 高 橋 明 夫FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. 1...Package board, 2...Capity, 3...
・Bellet, 4... Brazing metal, 5... Ponding pad, 6... Internal electrode, 7... Wire, 8... Cap, 9... Low melting point glass, 10... Metallization Layer, 11...first layer, 12...second layer, 13...
external electrode. Agent Patent Attorney Akio Takahashi
Claims (1)
型半導体装置において、パッケージに形成されている電
極のうち少な、くとも外１部電擲がメタライズ層上に第
１１層としてコー（、ｙ：）も、しくは銅またはそれぞ
れを主成分とする合金大−着し１、該第１層上に第２層
として貴金属ｋｇして形成されている。こ１．とを管機
とする半導体装置・２．１ 貴金属が金であることを特
徴とする特許請求の範囲第１項記載の半導体装置。 ３、貴金属が銀である、午１．ζを特徴とする特許請求
の範囲第１項記載の半導体装置。[Scope of Claims] 11. In a chip carrier type semiconductor device made of ceramic and Tsukupanoji, at least one part of the electrodes formed in the package is coated as an eleventh layer on a metallized layer. y:) is also formed by depositing a large amount of noble metal (kg) or copper (kg) or an alloy having each as a main component as a second layer on the first layer. This 1. 2.1 The semiconductor device according to claim 1, wherein the noble metal is gold. 3. The precious metal is silver. 1. The semiconductor device according to claim 1, characterized in that ζ.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59050949A JPS60195952A (en) | 1984-03-19 | 1984-03-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59050949A JPS60195952A (en) | 1984-03-19 | 1984-03-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60195952A true JPS60195952A (en) | 1985-10-04 |
Family
ID=12873071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59050949A Pending JPS60195952A (en) | 1984-03-19 | 1984-03-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60195952A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6356996A (en) * | 1986-08-27 | 1988-03-11 | 京セラ株式会社 | Electronic parts with gold conductive layers |
-
1984
- 1984-03-19 JP JP59050949A patent/JPS60195952A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6356996A (en) * | 1986-08-27 | 1988-03-11 | 京セラ株式会社 | Electronic parts with gold conductive layers |
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