JPS60195100A - Treatment of indium phosphide crystal - Google Patents

Treatment of indium phosphide crystal

Info

Publication number
JPS60195100A
JPS60195100A JP5163284A JP5163284A JPS60195100A JP S60195100 A JPS60195100 A JP S60195100A JP 5163284 A JP5163284 A JP 5163284A JP 5163284 A JP5163284 A JP 5163284A JP S60195100 A JPS60195100 A JP S60195100A
Authority
JP
Japan
Prior art keywords
indium phosphide
silicon
temperature
implanted
treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5163284A
Other languages
Japanese (ja)
Inventor
Akio Hayafuji
早藤　紀生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5163284A priority Critical patent/JPS60195100A/en
Publication of JPS60195100A publication Critical patent/JPS60195100A/en
Pending legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
    • C30B31/20—Doping by irradiation with electromagnetic waves or by particle radiation
    • C30B31/22—Doping by irradiation with electromagnetic waves or by particle radiation by ion-implantation

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Inorganic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE:To form a highly concentrated n type layer of indium phosphide, easily, by carrying out the ion implantation of silicon to the surface of an indium phosphide crystal, and heating and activating the silicon-implanted layer of the indium phosphide crystal at a specific temperature. CONSTITUTION:The indium phosphide substrate 1 implanted with silicon ion is held by the holder 2, put into an electrical furnace composed of a quartz tube 4 surrounded by an electrical heater coil 5, and annealed in hydrogen gas atmosphere. The above treatment is carried out by raising the temperature of the silicon-implanted layer to 650-700 deg.C by the resistance heating with the electrical heater coil 5 measuring the temperature by the thermocouple 3, and preferably holding the system at the maximum temperature for 20-60min. The substrate 1 is activated by this treatment, and a high-concentration n type layer having a sheet carrier concentration of about >=10<13>cm<-2> can be produced easily.

Description

【発明の詳細な説明】 この発明は、リン化インジュウムの高濃度ｎ型層の形成
に関するものである。DETAILED DESCRIPTION OF THE INVENTION This invention relates to the formation of a highly concentrated n-type layer of indium phosphide.

イオン注入法は、半導体結晶表面にイオン注入して、電
気伝導層を形成するのに有効な手段であり、近年は、シ
リコンのみならず化合物半導体′の分野にも広く用いら
ｎるようになってきた。このとき注入イオンの活性化の
ため、注入後にア二−／ｌ／ｉ行なう必要があり、この
技術の確立がイオン注入法？用いる場合の重要、咀とな
っている。The ion implantation method is an effective means of implanting ions into the surface of a semiconductor crystal to form an electrically conductive layer, and in recent years it has come to be widely used not only in the field of silicon but also in the field of compound semiconductors. It's here. At this time, in order to activate the implanted ions, it is necessary to perform ani-/l/i after implantation, and the establishment of this technology is the ion implantation method. It is important when using it, it is chewing.

リン化インジュウムは制周波・高出力の電解効果トグン
ジスターや光素子用として期待さ几ている化合物半導体
材料である。リン化インジュウムの高濃度ｎ型層は、こ
のような半導体素子において・金属電極とのオーミック
接触ｒ形成する部分に用いら扛る。Indium phosphide is a compound semiconductor material that is expected to be used in frequency-controlling, high-power field effect tongisters and optical devices. In such a semiconductor device, a high concentration n-type layer of indium phosphide is used in a portion where an ohmic contact with a metal electrode is formed.

半絶縁性リン化インジュウム基板の表面に晶濃度ｎ型層
？形成するには、シリコンイオンケ注入する場合が多い
が、このときの適切なアニール方法とその条件はまだ充
分な検討がなされていない。Crystal concentration n-type layer on the surface of a semi-insulating indium phosphide substrate? Although silicon ion implantation is often used to form this structure, the appropriate annealing method and conditions have not yet been sufficiently studied.

この発明は、上記のような問題点にもとづき、シリコン
ケイオン注入したリン化インジュウム基板のアニール方
法とその条件？検討して得らｒｔ＊ものであり、リン化
インジュウムの高濃度ｎ型層ヶ得るためのアニール方法
とその条件會提供するものである。This invention is based on the above-mentioned problems, and proposes an annealing method and conditions for an indium phosphide substrate implanted with silicon ions. This is an rt* product obtained through investigation, and provides an annealing method and conditions for obtaining a high concentration n-type layer of indium phosphide.

以下、この発明の一実施例？詳細に説明する。Is the following an example of this invention? Explain in detail.

第１図は、本発明によるアニーｌし方法ケ説明した図で
ある。図中（１）はシリコンケイオン注入したリン化イ
ンジュウム基板、（２）は基板の支持具、（３）は温度
モニター用の熱電対、（４）は石英管、（５）は抵抗−
加Ｐ電熱コイルである。この装ｆｆ＆では水素ガス雰囲
気中にリン化インジュウム基板（１）ｒ保持しておき電
熱コイル（５）を用いた抵抗加熱によってリン化インジ
ュウム基板ヶ高温にし、シリコンイオン注入層のてニー
ルを行うものである。第２図は、シリコンケイオン注入
したリン化インジュウム基板ケ第１図に記した装置によ
ってアニールし、高温度ｎ型層？得るのに必要な湿度プ
ロファイル會示している。ここで重要なものは、図中に
示したアニール温度Ｔａ（Ｃ）と７二一ル時間ｔａＣ分
）である。FIG. 1 is a diagram illustrating an annealing method according to the present invention. In the figure, (1) is an indium phosphide substrate implanted with silicon ions, (2) is a support for the substrate, (3) is a thermocouple for temperature monitoring, (4) is a quartz tube, and (5) is a resistor.
It is a heating coil. In this setup, the indium phosphide substrate (1) is held in a hydrogen gas atmosphere, the indium phosphide substrate (1) is heated to a high temperature by resistance heating using an electric heating coil (5), and the silicon ion-implanted layer is annealed. It is. Figure 2 shows an indium phosphide substrate into which silicon ions have been implanted, which is then annealed using the apparatus shown in Figure 1 to form a high-temperature n-type layer. It shows the humidity profile required to obtain. What is important here is the annealing temperature Ta(C) and the time taC minutes shown in the figure.

第８図は、アニール時間ｔａＱ２０分とした時、アニー
ル温度Ｔａ　を変えて、注入したシリコンイオンの活性
化の様子を注入量に対してプロットした実験結果である
。FIG. 8 shows experimental results in which the activation of implanted silicon ions is plotted against the implantation amount by varying the annealing temperature Ta when the annealing time taQ is 20 minutes.

’ｒａ　＝？　Ｏ０℃としたときには、注入量が１０′
４０−雪の高濃度領域まで１００％に近い活性化率が得
られるのに対して、Ｔａ　＝　６．５０　Ｃ未満のとき
には、注入量１０”　ｃｍ−”以上の高温度域で注入し
たシリコンイオンが充分に活性化さｎていない。'ra=? When the temperature is O0℃, the injection amount is 10'
40-Although an activation rate close to 100% is obtained up to the high concentration region of snow, when Ta = less than 6.50 C, silicon ions implanted at a high temperature range with an implantation amount of 10"cm-" or more is not activated sufficiently.

Ｔａ　＝　７５０　Ｃとすると、リン化インジュウム基
板に荒れがみらｎるようになり、活性化率も１００％を
超える部分が多くおるなど異常な挙動ケ示すようになる
。従って、この場合高濃度ｎ型層を得るには、６５０Ｃ
以上７００Ｃ以下の狭い温度でアニール會行う必要があ
る。第４図は、注入したシリコンイオンの活性化率會ア
ニール時間に対してプロットした実験結果である。なお
注入量は１０”　ｃｍ＝である。以上の実験においては
アニール時のリンの解離蒸発ケ防ぐために、リン化イン
ジェウム基板表面はリンガラス膜で保護しである。When Ta = 750 C, the indium phosphide substrate begins to show roughness and exhibits abnormal behavior, with many parts having an activation rate exceeding 100%. Therefore, in this case, to obtain a high concentration n-type layer, 650C
It is necessary to carry out the annealing at a narrow temperature of 700C or less. FIG. 4 shows experimental results plotted against the activation rate of implanted silicon ions and annealing time. The implantation amount was 10" cm. In the above experiments, the surface of the ingeium phosphide substrate was protected with a phosphorus glass film to prevent dissociation and evaporation of phosphorus during annealing.

本発明はシリコンケイオン注入したリン化インジュウム
基板において、シートキャリア濃度が１０’″（Ｍ”以
上の高濃度ｎ型層を容易に得ることができるアニール方
法を提供するものであり・リン化インジュウム結晶を用
いる半導体素子の製造工程に欠くことのできない重要な
技術を提供する。The present invention provides an annealing method that can easily obtain a highly concentrated n-type layer with a sheet carrier concentration of 10'''(M'' or more) in an indium phosphide substrate into which silicon ions are implanted.Indium phosphide crystal We provide important technology indispensable to the manufacturing process of semiconductor devices using

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は一本発明によるリン化インジュウム基板のアニ
ール方法を示す図、第２図は本発明による方法でリン化
インジュウム基板にアニールスル時の流度プロフフイ／
Ｌ’欠示す図、濱１図はｌｊ　”ｙｊ）コンイオン注入
量に対して、アニール温度ｔバヲメータとしてシートキ
ャリア濃度ｔプロットした実験結果である。第４図はシ
リコンイオン注入量１０１Ｆ＋”の試料についてシリコ
ンイオンの活性化率ｔアユ−３時間に対しプロットした
実験結果である。 １／中（１）（’ｊ：　Ｖ　！Ｊ　＝Ｉ　：ｙイオンを
注入したリン化インジュウム基板、＋２１は基板の支持
具、（３）は熱電対、（４）は石英管、（５）は電熱コ
イルである。 代理人　大岩増雄 第１図 第２図 時間（分） 第３図 Ｆ−ズ′童　（ｃｍ−２） 第４図 アニール杓閘　い）FIG. 1 is a diagram showing a method of annealing an indium phosphide substrate according to the present invention, and FIG.
The missing figure in L' and Figure Hama 1 are the experimental results in which the sheet carrier concentration t is plotted as annealing temperature t barometer against the lj ``yj)con ion implantation amount. Figure 4 is for a sample with a silicon ion implantation amount of 101F+''. These are experimental results plotted against the silicon ion activation rate tAyu-3 hours. 1/Middle (1) ('j: V!J = I:y Indium phosphide substrate implanted with ions, +21 is a support for the substrate, (3) is a thermocouple, (4) is a quartz tube, (5) is an electric heating coil. Agent Masuo Oiwa Figure 1 Figure 2 Time (minutes) Figure 3 F-Z' (cm-2) Figure 4 Annealing (cm-2)

Claims (3)

【特許請求の範囲】[Claims] （１）　シリコン？表面にイオン注入したリン化インジ
ュウム結晶において、シリコン注入層紮６５０Ｃ以上で
７００Ｃ以下の温度まで昇流して活性化子ること？特徴
とするリン化インジュウム結晶の処理方法。(1) Silicon? In an indium phosphide crystal with ions implanted into the surface, is it possible to raise the temperature of the silicon implanted layer to a temperature of 650C or higher and 700C or lower to form an activator? Characteristic processing method for indium phosphide crystals. （２）リン化インジュウム結晶が到達する最高温度にリ
ン化インジュウム結晶ケ保持する時間が２０分から６０
分の間であること？特徴とする特許請求の範囲第１項記
載のリン化インジュウム結晶の処理方法。(2) The time required to hold the indium phosphide crystal at the maximum temperature it reaches is 20 minutes to 60 minutes.
Being between minutes? A method for treating indium phosphide crystals according to claim 1. （３）　電気炉？用いる抵抗加熱により処理？行う(3) Electric furnace? Treatment by resistance heating? conduct
JP5163284A 1984-03-15 1984-03-15 Treatment of indium phosphide crystal Pending JPS60195100A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5163284A JPS60195100A (en) 1984-03-15 1984-03-15 Treatment of indium phosphide crystal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5163284A JPS60195100A (en) 1984-03-15 1984-03-15 Treatment of indium phosphide crystal

Publications (1)

Publication Number Publication Date
JPS60195100A true JPS60195100A (en) 1985-10-03

Family

ID=12892217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5163284A Pending JPS60195100A (en) 1984-03-15 1984-03-15 Treatment of indium phosphide crystal

Country Status (1)

Country Link
JP (1) JPS60195100A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02112236A (en) * 1988-10-21 1990-04-24 Nippon Mining Co Ltd Manufacture of compound semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02112236A (en) * 1988-10-21 1990-04-24 Nippon Mining Co Ltd Manufacture of compound semiconductor device

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