JPS6019473B2 - electronic clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece, and more particularly to an electronic timepiece equipped with a sound generator.

An object of the present invention is to confirm the operation of the operation switch with sound, and further, to generate the operation sound only when confirmation of the operation of the operation switch is necessary.

Recently, electronic watches that use liquid crystal display elements as display means have become popular, and it is expected that they will continue to become more affordable and multi-functional in the future.

Multi-functionality includes chronograph function, world clock function,
A computer bear can be considered, but the most practical and multi-functional option is an electronic clock with an alarm function. The present invention
The sound generator of this electronic watch with an alarm function is used to generate a "beep" sound in response to the operation of an operation switch such as a correction switch or a chronograph start/stop switch. By generating this operation sound, it is possible to visually confirm the operation of the operation switch, and the pleasant sound can be expected to have the psychological effect of giving the watch a sense of trust and a new sense of fun.

Embodiments will be described below with reference to the drawings included in the examples.

FIG. 1 is a block diagram of an electronic timepiece according to the present invention having an alarm function and a chronograph function. 1 is a time standard source such as a crystal oscillator, and 2 is a block diagram for converting the signal of the time standard source into IHZ. Frequency dividing circuit that divides the frequency up to 3 is 1/6
0 second frequency divider circuit, division frequency divider circuit, and 1/12 time frequency divider circuit, 7 is an alarm time setting counter (with memory function), 9 is the time of frequency divider circuit 3 and alarm time setting counter 8 is a chronograph frequency dividing circuit. 13 is a mode (function) switching switch SW for selecting time functions, that is, basic clock mode, alarm time setting mode, stopwatch mode, etc.; 14 is a switch SW for changing time functions in time correction mode and alarm time setting mode; SW2 and SW15, which play the role of digit selection switch, i.e., select switch, and start/stop switch in chronograph mode, add the correct/selected digit each time the switch is operated in time correction mode and alarm time setting mode. The switches SW3 and SW12, which also play the role of a set switch for resetting, and a wrap or reset switch in the chronograph mode, are control circuits that control the switch functions described above, each of the circuits described above, and the circuits described below.

4 is a display switch that selects the input to the decoder drive circuit 5 from the hour, minute, and second frequency divider circuit 3, alarm time setting counter 7, and chronograph frequency divider circuit 8 by outputs M, , M2 to the mode counter, which will be described later. The circuit 6 is a liquid crystal display means.

Reference numeral 11 denotes a sound device, and 11 is a sound generator control circuit that causes the sound generator 11 to generate sound.

Figure 12 shows the control circuit 1 in the block diagram of Figure 1.
2, a part of the sound generator control circuit 10, and the sound generator 1
1 is a detailed circuit diagram of FIG.

Block A in the figure is a chattering prevention and waveform shaping circuit that shapes input signals from switches 13 to 15, and block B is a mode counter that receives the output of the waveform shaping circuit and generates mode signals M, M2. selection circuit,
C is a sound generator control circuit, and D is a sound generator. FIG. 3 shows a specific circuit of the flip-flop (FF) used in FIG. 2, in which 38-41 are clocked gate inverters and 42-44 are inverters.

The clocked gate inverters 38 and 41 are in an operating state when CL (clock) is High, and are in an inoperable state when the clock is high.
Low indicates an operating state, and High indicates a non-operating state. Therefore, the MASTER section writes the signal from W when CL is high, and enters the hold state when CL is low, and the SLA
The VE section writes a signal from W at CL-Low, and enters a hold state when CL-Low is reached. FIG. 4 is a timing chart of voltages at various parts in FIG.

In Fig. 2, 16 of block A is a MOS resistor for pull-down resistance, and 17 and 19 are MASTE resistors shown in Fig. 3.
The R-type FF 18 is a SLAVE-type FF, and each FF operates with a 64Hz clock.

Waveform shaping is performed with FF17-19, and NAND gate 25, A
The ND gates 26 and 27 divide the pulse into 1/12 mirror sand pulses. FF23 and 24 of Flock B are MAS of FF in Figure 3.
Connect TER output Q and SLAVE input W,
1/1 which connects output Q and MASTER input W respectively.
It is a divide-by-2 circuit, and its outputs M, M2 have 4 modes: LL is the basic clock mode, L is the chronograph mode, HL is the alarm time setting mode, and HL is the alarm time setting mode. Indicates each state of the time adjustment mode of the basic clock. In block C, 33 is an OR gate for generating sound no matter which switch SW2 or SW3 is turned on;
32 is an OR gate for detecting the basic clock mode state (M, ground is LL state), and 28 is an ○R gate that operates SW2 or SW3 when detecting that the gate 32 is in the basic clock mode. This is an AND gate that prevents sound from being generated even when the The AND gate 29 receives the output a of the alarm coincidence detection circuit shown in FIG.
An OR signal f of the output d (switch operation system) of the AND gate 29 and the output e (alarm coincidence system) of the AND gate 29 is generated. 2 0
is SLAVE type FF, 2 1 is MASTER type FF, 2
2 is a SLAVE type FF, and the output of each is Q,,
Let them be Q2 and Q3.

The FFs 20 to 22 form a delay circuit clocked at 8 Hz, and the combination of the FFs and the AND gate 30 limits the sound generation time width to 125 ms as shown in the timing chart of FIG. However, the sound generation time due to the switch operation, that is, the operation sound, is 62.5 ms to 125 ms depending on the timing of the switch operation. The AND gate 31 is a modulation gate, and in this embodiment, the modulation frequency is the intermediate output 4096Hz of the frequency divider circuit 2 shown in the block diagram of FIG.

In block D of FIG. 2, 36 is a sound generator, which in this embodiment is an electromagnetic type puzzer. 35 is a driving NPN transistor, 37 is a resistor for absorbing the bounce voltage due to the inductance of the puzzer,
The resistance value is about lkQ.

In Figure 2, circuits not specified are complementary MOS・F.
The power supply is 3V except for block D due to the response voltage of the liquid crystal display element. In the same figure, the circuit consisting of gates 28 and 32 is SW2 or S
This corresponds to a prohibition circuit that selects whether or not to generate sound due to the operation of W3 depending on the mode, and the circuit consisting of FFs 20 to 22 and gate 30 corresponds to a sound generation time width control circuit. In this embodiment, a sound generation time width control circuit based on switch operation and a sound generation time width control circuit based on alarm coincidence are used in common.

To explain the timing chart in FIG. 4, OR gate 3
The output b of 2 is a peak w only when both M, , M2 are LOW, that is, in the basic clock mode.

When SW2 or SW3 is operated, the waveform is shaped and the output c of the OR gate 33 becomes High. If the mode is other than the basic clock mode, b is High, so the output f of the OR gate 34 is also High, and Q, , Q2, and Q are sequentially High in synchronization with the 8Hz clock, and the AND
A signal g having a pulse width of 12 shoes s is obtained by the gate 30. The signal g is 4096H by the modulation gate 31.
The signal h is modulated by Z, and is sent from the sound generator to SW2.
Alternatively, a beep sound is generated each time SW3 is operated. On the other hand, if the mode is basic clock mode, b
Therefore, AND gate 28 is prohibited and SW2, SW
There is no operation sound even if you operate 3.

When the alarms match, a goes high, and the output e of the AND gate 29 and the output f' of the OR gate 34 become the same signal as IHZ, and the signal g goes high for 125 ms from the rise of the IHZ signal. Therefore, when an alarm matches, a sound of 4096 Hz is generated from the audio device in synchronization with the IHZ signal with a period of 1 second and a time width of 125 ms. Although the present invention has been described in detail with reference to the illustrated embodiments, the present invention is not limited to the illustrated embodiments, and various modifications and improvements can be made within the technical scope of the claims. It is something that can be achieved.

As described above, the electronic timepiece according to the present invention is one that generates an operation sound with a "ping" when necessary in response to the operation of an external operation switch, etc., and can confirm the operation with the sound. The operation can be confirmed by sound, and the generation of operation sound is automatically prevented in modes that do not require operation sound, such as the basic clock mode, thereby preventing bother and wasteful power consumption.

Furthermore, since the generation time width of the operation sound is controlled to be short, power consumption can be minimized in this respect as well.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an electronic timepiece according to the present invention. FIG. 2 is a detailed circuit diagram of a part of the control circuit of the electronic timepiece, the audio device control circuit, and the audio device shown in FIG. 1. Figure 3 shows
Detailed diagram of MASTER-SLAVEFF used in FIG. 2. FIG. 4 is a timing chart diagram of the main parts of the circuit of FIG. 2. 1... Time standard source, 2...
... Frequency dividing circuit, 3... Sand, minute, time dividing circuit, 4...
... Display switching circuit, 5 ... Decoder drive circuit, 6 ... Liquid crystal display means, 7 ...
- Alarm time setting counter, 8... Chronograph frequency dividing circuit, 9... Alarm coincidence detection circuit, 10... Sound generator control circuit, 11.
... Sound generator, 12 ... Control circuit. Figure 2 Figure 3 Figure Dimensions of the ship

Claims (1)

[Claims] 1. A time standard source, a frequency dividing circuit that divides the frequency of the signal of the time standard source, a display means that displays time based on the output of the frequency dividing circuit, a mode selection circuit for selecting a function, and controlling the mode selection circuit. In an electronic watch comprising a mode changeover switch, an operation switch that performs a predetermined function in the mode selected by the mode changeover switch, and a sound generator, when the operation switch is operated, the sound generation device generates an operation sound. A sound generation device control circuit is provided for making a warning sound, and the sound generation device control circuit includes a sound generation time width control circuit for driving the sound generation device only for a predetermined time after the operation switch is operated; 1. An electronic timepiece characterized in that the mode selection circuit comprises a prohibition circuit that prohibits the operator from generating an output when a predetermined mode is selected.