JPS60192538U - logic circuit - Google Patents
logic circuitInfo
- Publication number
- JPS60192538U JPS60192538U JP8130284U JP8130284U JPS60192538U JP S60192538 U JPS60192538 U JP S60192538U JP 8130284 U JP8130284 U JP 8130284U JP 8130284 U JP8130284 U JP 8130284U JP S60192538 U JPS60192538 U JP S60192538U
- Authority
- JP
- Japan
- Prior art keywords
- logic circuit
- gate
- gates
- inputs
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図、第２図は従来の論理回路を示す図、第３図は本
考案の一実施例による論理回路を示す図である。
図において、１は肯定否定出力素子、２，５は否定素子
、４，６はＯＲタイ、７はＡＮＩ）ゲート、８はＯＲゲ
ート、９は半導体スイッチ、１０は２値記憶素子、１１
は入力回路である。なお図中同丁符号は同−又は相当部
分を示す。
第３図
−1 and 2 are diagrams showing conventional logic circuits, and FIG. 3 is a diagram showing a logic circuit according to an embodiment of the present invention. In the figure, 1 is a positive/negative output element, 2 and 5 are negative elements, 4 and 6 are OR ties, 7 is an ANI) gate, 8 is an OR gate, 9 is a semiconductor switch, 10 is a binary storage element, and 11
is the input circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 3-
Claims (1)
数の論理積ゲートの出力の論理和を生成する論理和ゲー
トとを有する論理回路において、各論理積ゲートの各入
力回路に設けられた半導体−スイッチと、同じく該各入
力回路に設けられその記憶状態に応じて上記半導体スイ
ッチをオン・オフする書替え可能な２値記憶素子とを備
え、上記論理積の入力の組合せを変更可能であることを
特徴とする論理回路。In a logic circuit having a plurality of AND gates □ that generate an AND of inputs, and an OR gate that generates an OR of outputs of the plurality of AND gates, each input circuit of each AND gate is provided with a and a rewritable binary memory element which is also provided in each of the input circuits and turns on and off the semiconductor switch according to its storage state, and the combination of the inputs of the logical product can be changed. A logic circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8130284U JPS60192538U (en) | 1984-05-30 | 1984-05-30 | logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8130284U JPS60192538U (en) | 1984-05-30 | 1984-05-30 | logic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60192538U true JPS60192538U (en) | 1985-12-20 |
Family
ID=30627960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8130284U Pending JPS60192538U (en) | 1984-05-30 | 1984-05-30 | logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60192538U (en) |
-
1984
- 1984-05-30 JP JP8130284U patent/JPS60192538U/en active Pending
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