JPS6019243A - Loop test system - Google Patents

Abstract

PURPOSE:To check the faults of functions including a connection function for a concentrated data processing system by performing diagnosis while transmitting and receiving data by return by a terminal controller together with selection of an optional one of plural terminal devices. CONSTITUTION:The test data is transmitted from a terminal device 3aa and held by a register of a transmission/reception control part 22 via an input selector MPX23. In this case, the data holding signal DR is delivered from the part 22 to actuate the 2nd timer 28b. Then the transmission data load signal THRL is transmitted from an AND3 after a fixed time (1sec), and the test data held at the part 22 is transmitted to the device 3aa from a DVa via an output selector DEC24 in the form of the transmission data. The reception data are sent back by turn from the device 3aa. A counter 25 is counted up by the data transmission end signal TRE, and the combination of next RVb and DVb is selected. In the same way, the return test to be sent to the DVb is carried out repetitively while ''1'' is delivered from a test instruction part 27.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a return test method in a terminal control device that collects and distributes data from a plurality of terminal devices in a data processing system.

(b) Background of the technology Traditionally, in order for data processing systems to maintain the data processing functions expected in daily operations, the various devices that make up the system are periodically diagnosed, and any shortcomings are pointed out in the diagnosis results. If so, it is necessary to carry out repairs at a certain level.

(c) Prior Art and Problems Section 1 In Figure 0, which shows a conceptual diagram of the structure of a data processing system in the conventional technology and an embodiment of the present invention, 1 is a central processing unit t (CPU), and 2a to 2m are terminal controllers. Equipment (T
C) and 3aaNmn are terminal devices. The number of terminals [
3-aa"-mn is composed of a single model or a plurality of models. The CPU 1 is not shown in the figure, but as is well-known, it is usually a terminal control device under its own control or control as necessary according to the functions and programs it holds. 2a-m and terminal device 3aa=mn', but other terminal control devices 2a=m and terminal device 3aa-
Although mn has a failure display function, it does not have a self-diagnosis function. Therefore, in order to diagnose all devices in the system configuration at a certain level, it is best to use a method that allows the final diagnosis to be performed using the CPUI.%TC2a-m and terminal device 3aa
-mn is based on the method of connecting a separate testing device and executing the diagnosis.

The former maintains data processing tasks in the CPU l.
, interrupts and multiple +t'fjJT programs are required to execute the relevant diagnostic work, making the diagnostic operation cumbersome, or when the number of target devices for the diagnostic work ranges from several tens to several hundreds of terminal devices. The latter has the disadvantage of requiring a long time for diagnosis, and the latter does not reduce the data processing work of CPU1, but
(d) Object of the Invention The object of the present invention is to solve the above-mentioned disadvantages. To remove T02a-m and terminal device t without using the diagnostic function of CPU1.
Between 3aa-mn, one device of 'pc2a-m, for example, TC2a and a plurality of terminal devices 3aa=an connected to TC2a, are grouped, and the terminal devices 3aa-an are connected by maximizing the functions of TC2a. By providing a test method that selects an arbitrary terminal device and sends and receives data back and forth, the data processing capacity of the CPU 1 is not diminished, and the terminal device [3aa-
The present invention attempts to provide a means to enable interfering words including a connection function for mn and TC2a to TC2a to m.

(e) Structure of the Invention The object of the invention is to provide a group of terminal devices for inputting and outputting data and a plurality of terminal control devices for collecting and distributing data for each group of terminal devices, and for controlling the group by a central processing unit. In a data processing system, a terminal control device has a means for inputting and outputting data corresponding to a central processing unit, a means for separately inputting and outputting the data corresponding to a plurality of terminal devices, and a means for selecting the input and output means. The transmission/reception control means includes a transmission/reception control means for controlling data to the terminal device and a plurality of timer means for time-monitoring data transmission/reception, and the transmission/reception control means mutually controls the relay of data from the central processing unit to the terminal device in the transmission/reception mode. At the same time, in the test mode, the input means corresponding to the terminal device is finally selected and its data is held, and after a certain period of time set in advance by the timer means, the output means corresponding to the same terminal device is selected and the data is held. This can be achieved by providing a loopback test method characterized by retransmitting data and performing tests between a terminal control device and a plurality of terminal devices.

(f) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a block diagram of a folded test method according to an embodiment of the present invention. FIG. 3 shows a block diagram of a modified example using a fold-back test method in one embodiment of the present invention.
In the figure, 21 is the driver/near bar (DV/RV)
, 22 is a transmission/reception control unit, 23 is an input selector (MPX)
, 24 is an output selector (DEC), 25 is an address register/counter, 26 is a transmission/reception instruction section, 27 is a test instruction section,
28a is the first timer, 28b is the second timer, RVa-n
is line receiver, DVa-n is line driver, AN
D1 to D4 are flip-flop circuits. FIG. 2 shows an example of the configuration of TC2a, for example. The transmission/reception control unit 22 has a control function for relaying parallel data transmitted and received via the DV/RV 2L during normal transmission/reception operations in response to either the terminal device 3aaxmn, or in this example, the terminal device 3aa=an. It has a register function for data buffers and a data serial/parallel conversion function. Address register/counter 25
In normal data transmission/reception mode, DV/RV2
4g receives address data l from L, sends an address signal (ADD) to MPX23 and DEσ24, and RVa
In the 0 test mode, which selects one from =n and DVa-n, it operates as an address counter that is reset to zero when the first test mode is set, although it is not shown in the figure, similar to the initial setting performed when the power is turned on, etc. The O transmission/reception command section 26 advances in response to the input signal from AND5 and selects by applying a common ADD in the MPX 23 and DEC 24. While the data transmission/reception command mode is set, the test command section 27
each continuously sends out and holds an output signal 1 while the test mode is set. The m1 timer 28a inputs the set signal, continuously sends out the output signal l after a preset period of time, for example 10 seconds, and returns the output signal to 0 by the reset signal. The data length timer is a data length timer whose settings are updated by sending out an output signal 1 after a preset period of time, for example, one second, after inputting a set signal. One embodiment of the present invention is configured as described above, so that in the data transmission mode, the address register/counter 25 is set to ADD/AD by the address data input to the DV/RV 21 via the
The DEC24 sends the driver specified by ADD (
DV) is selected from DVa-n, and also in the reception mode in which the transmission/reception control unit 22 converts the transmission data into parallel/serial data and sends it to any of the terminal devices ft3aa~&n corresponding to the selected DV. A according to address data
By selecting MPX23 by DD, terminal equipment [3aa
- The transmission/reception control unit 22 executes serial/parallel conversion of the serial data sent by the operation of the an, and sends it to/< via BY/DV2L. 1 is sent from the unit 26 and the first timer 28
a is activated, but the data holding signal (D R) indicating that the received data is set in the /buffer register of the transmission/reception control unit 22 is sent out and the device is reset, so the data reception operation is normal. In the running state, the first timer 28a will not output a 1.0 In the reception mode, if no data has been received for a certain period of time, in this case 10 seconds or more, the first timer 28a will output a 1. Then, a time elapsed signal (TOY) is sent from AND4. Although not shown, TOV is set in a latch circuit and sent to the bus, and serves as an interrupt signal to notify the CPU 1 of the end state of TCa2.At the same time, the second timer 28b is set by DR, and DR sends out After a certain period of time, in this case 1 second, output signal 1 is sent out and TOV is sent out via AND4 in the same way. The set state in the timer 28b continues to be updated, and the output signal is suppressed, and after a certain period of time from the state in which the final set is no longer present, the output signal 1 is sent out for a certain period of time one second later.

As described above, in the transmission/reception mode, the transmission/reception data goes through the DV/RV 21 and the CPU 1 intervenes in the operation.
Diagnosing an also required the operation of the CPUt. However, in this embodiment, the test instruction section 2 is used as the test mode.
After the address register/counter 25 is reset to O by holding the output of 1 from 7, ADD becomes MPX23.
0 is sent to the DEC 24 to select RVa and D'Va. In this state, the DV/RV 21 is inhibited from transmitting/receiving operations to the bus by the output signal from the test command unit 27. 0 Also, AND4 is also inhibited by this signal 0 Terminal device 3a
Send the test data by doing a and hold the test data in the register of the transmission/reception control section 22 via the MPX 23. At this point, DR is sent, the second timer 28b is activated, and after a certain period of 1 second, from AND 3 Transmit data load signal (
The test data (THRL) transmitted and held in the transmission/reception control unit 22 is transmitted as transmission data to the DVa via the DEC 24.
It is sent to the terminal device it3a a from the terminal device it3a.
oTRE, by which the received data from a is looped back, is a transmission completion signal for single or multiple serial data, and increments the address register/counter 25 to select the next combination of RVb and DVb. The received data is set in the transmission/reception control unit 22, and its DR
After a certain period of time set in the timer 28b, the return test, which is delayed by 1 second and sent to DVb, can be repeated as long as the test mode is set and 1 is output from the test command section 27. . Of course, depending on the data transmission speed, it goes without saying that the activation time from the timer set in the second timer 28b to sending out the output signal 1 can be arbitrarily set.The multiple timers used for transmission/reception control can be directly accessed by memory ( If there is a circuit available for use in the DMA (DMA) system, it may be used as a diversion.

Next, a modification of the present embodiment is shown in FIG. In this modification, the only difference is the setting method of the address register/counter 25, and everything else is the same. In this modification, the start of the address register/counter 25 is set to INV, FF2 . F'F3. AN
'The data extracted by DI and the single or multiple serial data transmission completion signal TRE are used as the FFI set signal, and the holding operation signal of register 24a=n, which is separately inserted between RVa-n and MPX23, is sent via ORI. This uses the Q output of the FF as a reset signal.

Terminal equipment (li3aa~an or sending/receiving t911 (#
The test data feedback function seen from the section 22 can be practiced and performed in the same manner as in the previous embodiment.

Although the above has been explained using Tea and the terminal devices aa to an under its control, it can be similarly implemented in other TCb-n. Further, the relationship between TCa=n is variable...It goes without saying that other combinations can be similarly realized as long as there is a control function.

(g) As described in detail, according to the present invention, it is possible to perform diagnosis such as troubleshooting in TCa~n and the terminal devices 3aa~mn under its control without setting the test mode and activating the CPUI. This is useful because it provides a possible repeat test method.

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram of the configuration of a data processing system in a conventional system and an embodiment of the present invention, Fig. 2 is a block diagram of a folded test method in an embodiment of the present invention, and Fig. 3 is a block diagram of a modified example thereof. ◇ In the figure, [ is central processing [7 (CPU)], 2a"m is '
N4 ”Ai ftflJ armor 3aa ~+nn, 2
1 is a driver, 7-bar (DV/RV), 22 is a transmission/reception control unit, 23 is an input selection 5 (MPX), 24 is an output selector (DEC), 26 is a transmission/reception command unit, 27 is a test an instruction section; 28a is a first timer; 28b is a second timer;
RVa-n is a line reinover and T'+Va-n is a line driver.

Claims (1)

[Claims] In a collective data processing system that has multiple terminal devices that input and output data and multiple terminal control devices that collect and distribute data for each group of terminal devices, and is controlled by a central processing unit, the terminal control device is centrally controlled. A means for inputting and outputting data corresponding to a processing device, a means for separately inputting and outputting the data corresponding to a plurality of terminal devices, and a transmission/reception control for selecting the input and output means and controlling data to the terminal device. and a plurality of timer means for time-monitoring the transmission and reception of data, and the transmission and reception control means mutually controls the relay of data from the central processing unit to the terminal device in the transmission and reception mode, and also controls the relay of data from the central processing unit to the terminal device in the test mode. selects the input means corresponding to the same terminal device and holds the data, selects the output means corresponding to the same terminal device after a certain period of time set in advance by the timer means and resends the held data, A return test method characterized by executing tests between terminal devices.