JPS60191330A - Security system of data accuracy for operation - Google Patents

Abstract

PURPOSE:To obtain the information on data comparison for each operation and to check the security of accuracy for the final result, by recording the minimum length of a mantissa part with a series of operations where plural expressions are used for variation of the length of an exponent part through fixture of data length. CONSTITUTION:The input data 1 is supplied to each operator 3 within a computer, and the output data 2 of the operator 3 is delivered to an output line. At the same time, the data 2 is supplied to detection circuit 4 for length of a mantissa part. The circuit 4 consists of a shift register, etc. and detects the number of mantissa parts of the data 2. The number of said mantissa parts is supplied to a comparator 6 for comparison with the signal applied from a register 5 through a signal line 8. Then the minimum length of the mantissa part is recorded in a series of operations, and the information on data comparison is obtained for each operation for check of accuracy security with the final result.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to guaranteeing the accuracy of calculations performed within a computer, and particularly to extracting information suitable for calculating relative accuracy.

[Background of the invention]

In conventional fixed-point or floating-point arithmetic, when an underflow (or overflow) occurs, an interrupt is used to notify the program of the situation. However, with these methods, underflows and autoflows (-flows) occur frequently, and the processing has to be interrupted each time. Several numerical expression methods have been devised to solve these problems. , oats (-) has been confirmed to not occur (see, for example, Transactions of the Information Processing Society of Japan, Vol. 24, No. 2).

However, such numerical representation is realized by using a variable-length exponent part (therefore, the mantissa part is also variable) inside fixed-length data. Therefore, the reliability of data obtained as the final result of a series of calculation flows becomes a problem.

[Purpose of the invention]

An object of the present invention is to provide information on the accuracy of data obtained as a result of a series of operations in a numerical expression with a fixed data length and a variable exponent length. In arithmetic units that have been used as black boxes, when using a numerical expression method that virtually does not cause overflow or underflow, the precision information of the numerical values that appear in the course of a series of calculations is stored, and the information can be changed according to the user's request. By making it possible to read information, the reliability of calculation results is guaranteed.

[Embodiments of the invention]

An embodiment of the present invention will be described below.

First, an example of numerical expression to which the present invention is applied will be described (see Journal of the Information Processing Society of Japan, Vol. 24, No. 2).

Let X be the number to represent. It is expressed as X=2°×f and two numbers e and f. Here, to make the value unique, e,
The following conditions are set for f. First, consider the case where X〉0.

e: Integer 1 × f < 2 At this time, the representation method in the computer is shown in Figure 1, but as far as this point is concerned, it is the same as many floating point representations, and the sign part S (: Sign bit ), the exponent part E (: Bxp
onent part ), mantissa part F (: prac
tionpart). Let the binary representation of the value of the mantissa f be as follows. f=l, flf,...f,...
・. At this time, let f, f2...f,... be the bit bumps of the mantissa part F.

The following method is used in which the exponent part E has a variable length and the length of the data field has self-descriptive ability.

Since the double exponential expression will be frequently used hereinafter, the following expression will be used to prevent the occurrence of printing-F errors.

2″c) exp(n) First, when e>0, the range where e can be represented by exactly binary mDO) digits is as follows.

If expressed in the range of 2 = '< e <2'' - 1 X, then e Considering the gender, exp(-2'
'') <x<exp (-2-'), -2"<8<-2'"-1, and complement representation is used.

The internal representation of the integer e when e is represented by exactly m binary digits is as follows.

When e>0, 00...01 e,, -s ''・e
! When ele〈0, 11...10eyu-1...
e2e.

From m and eyu-0...e2e defined here, add the identification pit row of m to the left and make the exponent part as follows.When it is 0, 0...01 e,, -,...e, e.

x (Similarly, the exponent and mantissa parts are defined for Q.

Now, FIG. 2 shows an example of the configuration of the present invention.

3 is each arithmetic unit existing in the computer. 1 is a signal line through which input data to the arithmetic unit flows, and 2 is a signal line through which output data from the arithmetic unit flows, and this data is also provided to the mantissa length detection circuit 4 at the same time as it is output. This mantissa length detection circuit 4 is mainly composed of a shift register or the like, and is a circuit for detecting the mantissa length of data applied via the signal line 2.

In this numerical representation, as described above, the calculation of the mantissa length is performed by detecting a break in a run of 0 or 1, and this can be easily constructed using a shift register, a counter, etc. FIG. 3 shows an example of its configuration. 18 is a shift register, 19 is a color register, and 20 is an element that performs an exclusive OR (XOFL). signal m1
The first bit of the data given by the signal line 2 is sequentially given to the signal line 5, and the nth pit output from the shift register is sequentially given to the signal line 16, and the result of their exclusive OR is as follows.
The signal is applied to a counter 19 via a signal line 17. The counter 19 counts up until it receives 0 from the signal line 17 for the first time. This determines the exponent length and therefore also the mantissa length (since the whole is of fixed length).

Returning to FIG. 2, a signal line 7 is a signal line through which the mantissa length detected by the mantissa length detection circuit 4 flows, and a signal line 8 is a signal line through which data already latched in the register flows. 6 is a comparison circuit that outputs the smaller of the data given by each signal line 7.8, and the result is sent back to signal line 1.
1 and is applied to register 5. 9 is a signal line through which signals for turning on/off, setting, and setting the register flow;
0 is a signal line that takes out the data held in the register 5 to the outside.

Next, an example of the operation of this embodiment will be explained. The user resets the register 5 using the signal line 9 prior to a series of operations. At the time of reset, the value of register 5 is set to +M (the maximum value that the mantissa length can handle).

Thereafter, the mantissa part of the operation result in the arithmetic unit 3 is given to the comparison circuit 6, the data that was already latched is given to 6 by 8, and the smaller of the two is outputted by 11 and latched into the register 5 again. be done.

This operation continues every time the calculation result is output from the calculation unit and until the user resets the signal line 9.

Therefore, the user can freely set the period for a series of calculations, and the contents of the register 5 can be read out via the signal line 10 as necessary.

〔Effect of the invention〕

According to the present invention, in a series of calculations, it is possible to capture not only the final result but also the size information of the data appearing for each calculation, so it is possible to verify the accuracy guarantee of the final result.

Furthermore, even if the results of the same operation differ due to the order of operations, a more desirable order of operations can be determined by the value of this register.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of numerical representation in a computer, FIG. 2 is a block diagram of the present invention, and FIG. 3 is a block diagram of a detection circuit for an exponent part and a mantissa part.

Claims (1)

[Claims] Data in operations, in an arithmetic unit consisting of an adder, a multiplier, etc., characterized in that a register is provided for recording the minimum value of the mantissa length in a series of operations using a numerical expression with a fixed data length and a variable exponent length. Accuracy guarantee method.