JPS63255735A - Floating-point multiplier - Google Patents

Abstract

PURPOSE:To make a circuit small-sized and economical by providing a means which suppresses the word length of an exponent part operating circuit to a required minimum bit width to prevent the malfunction even at the time of overflow and underflow of the exponent part. CONSTITUTION:Exponent parts EA and EB of a multiplier A and a multiplicand B are inputted to an exponent part adding circuit 31 to perform the addition processing. If underflow is detected in the addition result by a detecting circuit 32, the detection signal is outputted as a carry signal to a subtracting circuit 40. The subtracting circuit 40 adds +1 after adding -1 to input data and outputs data of the adding circuit 31 as the result as it is. Therefore, two inputs of a selecting circuit 53 are output data of the adding circuit 31 together and are equal to each other even if underflow occurs in the exponent part. Consequently, the malfunction does not occur though the normalization processing is performed in the mantissa part.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a parallel floating point multiplier that realizes high-speed multiplication, particularly a floating point multiplier that handles normalized data in two's complement representation. Market related to.

(Prior art) Floating Komaki point numbers, which are numbers expressed in floating point format, have a wide dynamic range and can be manipulated without maintaining a certain level of precision, so they are widely used in fields such as general-purpose computers. . In recent years, in the field of digital signal processing,
Since the need for real-time processing requires faster calculation times, multipliers that perform parallel multiplication are increasingly being provided in addition to arithmetic units that perform addition and subtraction. Such multipliers are realized using semiconductor integrated circuits.

This type of floating point multiplier is disclosed in Japanese Patent Application Laid-Open No. 59-140, for example.
This is disclosed in Japanese Patent No. 560, and an example of its configuration is shown in FIG. This multiplier includes a multiplier circuit 10 that multiplies the mantissa of a multiplier A in floating point format by a mantissa 88 of a multiplicand B in floating point format, and a normalization circuit 20 that normalizes the multiplication result of this multiplier circuit 10. , an addition circuit 30 that hnnv the exponent [8 and the exponent EB of the multiplicand B and a predetermined constant t') to the multiplier, and a subtraction circuit 40 that subtracts 1 from the tightening result of the 0 cotton circuit 30 (or (addition circuit that adds)
and a selection circuit 50 that selects and outputs either the output of the addition circuit 30 or the output of the subtraction circuit 40 based on the multiplication result of the multiplication circuit 10, and outputs the product in floating point format to the output of the selection circuit 50. The exponent is 19, and the mantissa is obtained from the output of the normalization circuit 20. In addition, the clip circuit 6 is installed in case overflow or underflow occurs.
0°70 is provided. A shift detection circuit 11 is attached to the multiplication circuit 10, and a normalization circuit 20 and a selection circuit 50 are controlled according to the output thereof as described later.

,,The selection circuit 50 includes an abnormality detection circuit 5 that detects overflow (OVF) or underflow (IJNF).
1 is attached, and its output controls the clip circuits 60° and 70.

Let us now consider the case where a floating point number is expressed in two's complement format. Assuming that the imperial court of numerical data is 32 pits I~,
It is assumed that 24 bits of these represent the mantissa M, and 8 bits represent the exponent F. In that case, 2/I of the mantissa M
Each of the 8 bits of bit and exponent E includes 1 sign bit or d3, the 14 bits of the mantissa are SF, and the 14 bits of the exponent are SN, 5E-Q, 5
) l = Q represents positive, and 5F = 1° 5) l = 1 represents negative. The exponent E is in the range -128≦F<127, and the mantissa M is for normalized data, so
The range is 0.5≦M<1, and the actual data value is (-1)・M・2(-1)-8F-F...(
1)S)! is given by

When the sum of multiplier A and multiplicand B is C=△・B, C=A −8 1to, )SA−HA−2(−1) ・SA・FA3moromi,,SR,M8.2( -1)・5R-EB)= (-1
) 8 8 B・ (to 1・Total IB) x 2f (-1)
・SA・FA+ (-1) ・513- FB
)...(2) (where ■ represents exclusive OR), and the mantissa HC and exponent HEt of the product C are respectively MC-(-osA
esB・(HA−)1B) ...(3) HE=
((-1)・SA -FA+ (-1)・S8・El
...It is expressed as (4).

If we follow the process of cylinder manufacturing in equations (3) and (4) in order in Figure 2, first, in the mantissa part, the mantissa H of the multiplier A.
A and the coefficient H8 of the multiplicand B are subjected to the cylinder forming process of equation (3) in the east circuit 10. At this time, 0.5≦M<1
．． Since 0.5≦MB<1, NC=HA・TO1B becomes 0.25≦HC<1, so 0.25≦)Ic<
0.5, the H8B output is set to M in the multiplication circuit 10.
It is necessary to perform a normalization shift with SB=O.

The fact that H3f3=o is detected by the shift detection circuit 11, and the normalization circuit 20 performs a 1-bit shift process to the left (higher digit), and roughly calculates 1 from the cylinder manufacturing result of the exponent part according to equation (4). Is there a need to reduce it?

A subtraction circuit 40 is provided to perform this process of subtracting 1, and a selection circuit 50 selects one of the output of the addition circuit 30 and the output obtained by subtracting 1 from it according to the output of the shift detection circuit 11. Choose the option.

An abnormality detection circuit 51 monitors whether there is an overflow or underflow in the output of the selection circuit 50, and if there is an overflow or underflow, a clipping process or exponent part clipping circuit 60 that performs replacement with the maximum value or minimum value; A clipping circuit 70 for the mantissa is performed.

Is this an abnormality detection in the exponent part operation in a floating point multiplier with such a configuration?
0, and the operation word length of the selection circuit 50 is extended by 2 bits higher than the word length of the input data 1, that is, the exponents EA and FB, and the abnormality detection circuit 51 calculates the upper 2 bits and the sign bit according to the circumstances. This was done by monitoring 3 bits.

3 to 6 show processing examples 1 to 4 for measuring abnormality detection modes in conventional index part processing in various cases.

The exponent EA in Fig. 3 is a 7-bit pinary data “11
11110” (126 in decimal Omotesawa, i.e. (+1
26) equivalent to 10) and 1 bit code data “1゛’
Therefore, the exponent EB has a value of 126-128 = -2, or (-2) 1o, in decimal representation, and similarly, the exponent EB has a value of 124-128--4, or (-4) 1o, in decimal representation. and EC= FA+ FB= (-2)10
FIG. 3 basically shows that +(-4)10=(-6)10. However, in FIG. 3, each code bit is expanded by two bits in the upper part of the exponents EA and FB, and "11" is added corresponding to the code "1". An extra addition operation is performed for this purpose. Looking at the abnormality detection bit, which consists of a total of 3 bits, 2 extension bits and a sign bit, in this addition result, it is “111”.
It can be seen that the calculation result is also the same value for all 3 bits within 8 bits, and there is no change before and after the calculation. This is considered normal.

Figure 4 shows EA = (0-128) IQ = (-128)
1o, E B = (0-128) = (-128)
In the case of 1o, if), the calculation result is FC = EA + F
This shows the case where B=(-128-128)10-(-256)10, which exceeds the 8-bit range.

In this case, since the sign bit changes before and after the operation, the three monitoring bits do not have the same value, resulting in underflow detection.

Also, if the sign extension bit is reduced to 1 bit, only 2 monitoring bits will be required, or this may result in false detection. As shown in Figure 5, this is the index FA,
Minimum value of 8 bits for both FBs (-128) = (0
-128) If it is 10, the abnormality detection bit of the operation result is "00pa" and underflow is detected. If the data causes a normalization shift in the mantissa part, the normalization shift processing is performed as shown in the figure. As a result, the abnormality detection bit becomes (41111), indicating overflow detection.

This is the maximum value of 8 bits (+127) 1o shown in Figure 6.
Abnormality detection bit “11'' that produces the result of double addition
This is the same as the overflow detection shown above, and it is impossible to distinguish between the two.

(Problem to be Solved by the Invention) However, in the floating point multiplier with the above configuration, the number of bits of the exponent part operation word length is set to 2 bits more than the number of input data pits in order to correctly detect an abnormality in the exponent part operation. Therefore, there was a problem in that the scale of the h0 arithmetic circuit, subtraction circuit, selection circuit, etc. provided in the exponent part became large.

The present invention solves the problems that the prior art had, by suppressing the word length of the exponent calculation circuit to the necessary minimum without affecting the critical path of the circuit delay time of multiplication processing.
This provides a floating point multiplier that solves the problem of difficulty in suppressing the increase in the size of the arithmetic circuit.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a multiplication circuit that multiplies the mantissas of a multiplier and a multiplicand in normalized floating point format, and an exponent of the multiplier and the multiplicand. In a floating-point multiplier that is equipped with an adder circuit that adds together two numbers, a subtracter circuit that subtracts 1 from the h-day calculation result of the adder circuit with a word length that is 1 bit longer than the exponent bit, and a subtracter that subtracts based on the output of the adder circuit. and control means for controlling the output of the circuit to be equal to the input of the subtraction circuit.

(Function) According to the present invention, since the floating point multiplier is configured as described above, even if the input data is j such that an underflow or overflow occurs in the exponent part, the abnormality detection bit can be detected through the control circuit. In addition, in the abnormality detection section of the present invention, the word length of the operator circuit is suppressed to the minimum necessary bit width, so that it is possible to prevent the circuit scale from increasing, and to improve the present invention. Accordingly, the critical path of the circuit delay time in the multiplication process is not particularly affected, and the east line processing speed is not adversely affected. Therefore, the above-mentioned problem can be eliminated.

(Example) FIG. 1 shows an example of the present defense.

On the mantissa side of the multiplier in FIG. 1, the multiplier circuit 10, shift detection circuit 11, and normalization circuit 20 are necessarily the same as those in FIG. The clip circuit 71 is different from the one shown in FIG. 2 in that two types of clip control 11 signals, one for exponent overflow and one for exponent underflow, are input. On the exponent part side, according to the present invention, the reservoir word length sign-extended to one bit higher than the data 8t (length) of the input exponents FA and EB is adopted as the word length of all the calculation parts. The basic functions of the tightening circuit 31, selection circuit 53, cl-3, and clipping circuit 61 are different from those in FIG. 2, respectively.
, selection circuit 50, and clipping circuit 60.

Note that underflow in the exponent part is detected by an underflow detection circuit 32 attached to the addition circuit 31, and the detection signal is sent as a control signal to the subtraction circuit 40 and both clip circuits 61 and 71. Overflow occurs in the selection circuit 53
This is performed by the overflow detection circuit 54 attached to the overflow detection circuit 54, and its detection signal is sent as a control signal to both clip circuits 61 and 71.

Now, let us consider the calculation cylinder processing in the multiplier of FIG. 1 in terms of numerical data in a two's complement display format with an 8-bit exponent and a 24-bit mantissa, as in the case of FIG. 2. First, when the east P7IA and the exponents FA and EB of the multiplicand B are inputted to the adder circuit 31 of the exponent part, the processing of the rabbit is performed here. Regarding the addition result, the underflow detection circuit 32 monitors a total of 2 bits, the original sign bit and 1 bit of sign extension bit, and when it detects that an underflow has occurred, the detection signal is It is sent to the carry input terminal of the subtraction circuit 40 as a carry signal. Functionally, the subtraction circuit 40 is a circuit that subtracts 1 from input data, and in terms of hardware, it is a circuit that adds a fixed value of -1, so it must receive a carry signal from the underflow detection circuit 32. When input, the subtraction circuit 40 operates to add -1 to the input data and then add +1 again, and as a result, outputs the output data of the addition circuit 31 as is.For this reason, the exponent part is underunder. When a flow occurs, the two inputs of the selection circuit 53 are both the output data of the adder circuit 31 and are equal to each other.
Even if normalization processing is performed on the mantissa part, as seen in the example of FIG. 5, no malfunction will occur. If underflow does not occur in the exponent part, the subtraction circuit 40 operates to perform only subtraction processing, and the selection circuit 53 operates to perform addition circuit 31.
The data from the subtraction circuit 40 and the data from the addition circuit 31 plus -1 are input, and one of these two data is changed by the detection signal of the shift detection circuit 11. Selectively output.

The overflow detection circuit 54 monitors whether an overflow occurs in the output of the selection circuit 53 and sends the detection signal to the clip circuits 61 and 71. Overflow detection circuit 54 or underflow detection circuit 32
When an overflow or underflow of the exponent data is detected, the detection signal is sent to both clip circuits 6.
1.71, and a well-known clipping process is performed in which the bit pattern is changed to the minimum value data format at the time of underflow and to the maximum value data format at the time of overflow.

The critical bus of the circuit delay time of the multiplication device of FIG. 1 with the above configuration is 1
0-shift detection circuit 11-selection circuit 53-exponent overflow detection circuit 54-clip circuit 61 or 71, and does not lead to an increase in the delay time of the first path in the cylinder making circuit according to the present invention.

(Inventor: Sung Dynasty) As mentioned above, according to the present invention, the word length of the exponent cylinder making circuit can be suppressed to the minimum necessary bit width, and the floating ΦJyJ
The C1 circuit has a means to prevent malfunctions even in the event of an overflow or underflow of the exponent in the X-fault data nest escape logic. It is possible to use a floating point multiplier to provide the fastest possible operation.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the −, real, and capital sides of a floating-point multiplier according to the present invention, FIG. 2 is a circuit diagram of a conventional floating-point multiplier, and FIGS. 3, 4, 5, and FIG. 6 is an explanatory diagram showing an example of how the exponent part is changed by the latitude multiplier shown in FIG. 2. 10... multiplication circuit, 11... normalization shift detection circuit, 20... IT realization circuit, 31...
... υu circuit, 32 ... Ungu flow detection circuit, 4 () ... reduction circuit, 53 ...
...Selection (R circuit, 54...Overflow detection circuit, 61.71...Clip circuit. Applicant's agent Kyo Insermoto Nariki invention (Koyoru Floating Moon\Several point multiplication Circuit diagram of the device Fig. 1 Fig. 2 EA 1111111110 = (-2), EB 1111111100 = (-4), OE
CI l l I I I + 1010 = (-6
),,. Abnormal output bit = normal Fig. 3 Sand abnormal output bit (output bit = underflow) Conventional exponent part processing example 2 EA l 10000000 = (-7
28), 6E8 +10000000 = (-7
28),. Minor abnormality detection Bi Soto = Under! Flow 7 test output 1 Biut Wabit E, A OOO000000*(-1),
, l I I I I I I
I + abnormality bit = overflow tree 17 conventional finger i, 3 block shift L3 y 1 child Siri 3 Fig. 5

Claims (1)

[Scope of Claims] A floating-point multiplier comprising: a multiplication circuit that multiplies the mantissas of a multiplier and a multiplicand in normalized floating-point format, and an addition circuit that adds the exponents of the multiplier and the multiplicand, a subtraction circuit that subtracts 1 from the addition result of the addition circuit with a word length that is one bit longer than the number of bits of the exponent; and a subtraction circuit that makes the output of the subtraction circuit equal to the input of the subtraction circuit based on the output of the addition circuit. A floating point multiplier comprising: a control means for controlling.