JPS60189353A - Method and device for transmitting status information - Google Patents

Abstract

PURPOSE:To reduce the deterioration to a data transmission, and to execute smoothly the operation of a system by executing a vibrating operation only for a prescribed time of rise and fall of a status signal of each channel. CONSTITUTION:A code sequence (bm) is outputted from a modulo N adding circuit 1 of the transmitting part of a device, and added to a polarity inverting circuit 5 through a subtracting circuit 3 and a time slot delaying circuit 4. Also, status signals RS-A-RS-C of each channel A-C are supplied to monostable multivibrators 7-9 and 10-12 which trigger rise and fall, and the pulse of a prescribed time width of its rise and fall is generated and added to AND circuits 16-22. Also, timing signals phi1-phi3 and outputs of A, B and C pattern detectors 13-15 are provided to the circuits 16-22. Subsequently, a polarity inverting signal Vn from an OR circuit 23 is supplied to the circuit 5, vibrating operation is fed to a code sequence (dm) only for a prescribed time, the deterioration of data from a transmitter 6 is reduced and it is transmitted to the reception side.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a time division multiplex transmission system for multi-channel signals based on multi-level class ■partial response encoding, in which status information is transmitted to transmit status signals such as status indications of each channel. The present invention relates to a transmission method and apparatus.

[Prior art]

Conventional class V partial response (hereinafter referred to as class W)
A data transmission method using a coding method (abbreviated as P-R) is disclosed in, for example, Japanese Patent Application No. 57-26823 and Japanese Patent Application No. 57-0.
Although it is described in detail in the Mei MJi book No. 88987,
The transmission side temporarily disturbs the class IV P-R encoding rule according to the status signal of each channel, and the reception side clearly distinguishes it from a violation of the Y P-R encoding rule due to a code error in the transmission path. Two consecutive violations that can be distinguished from each other and the received class W
By detecting a specific pattern caused by a violation operation on the transmitting side from the P-R code sequence, it is possible to detect the status signal for each channel. .

However, in conventional status information transmission methods, in order to transmit multi-channel status signals, when the transmission side increases the frequency of encoding rule violations in the original class mV P-R code sequence, class IV P-R The effect of suppressing DC components, which is one of the features of code sequences, is reduced, especially in single sideband communication systems (SSB-A) using amplitude modulation.
When applied to M), if the DC component of the baseband signal is insufficiently suppressed, the code error rate of the received code deteriorates.

[Summary of the invention]

Therefore, the object of the present invention is to perform a violation operation to prevent sending of status information only for a certain period of time after the rise and fall of the status signal of each channel on the transmitting side, and to perform the violation operation at other times. This inhibits the interference with the DC component suppression effect on class II/P-R code sequences, enables transmission of multi-channel status signals, and reduces the deterioration of the code error rate. An object of the present invention is to provide a status information transmission method and apparatus that realizes stable data transmission with a small number of errors.

In order to achieve such an object, the present invention provides a status information transmission method and apparatus for transmitting status information by intentionally giving a violation to a code sequence encoded by class ■ partial response encoding, and in which a block is transmitted on the transmitting side. When transmitting information for synchronization, polarity reversal control is performed continuously under the condition that a violation operation is performed only when a predetermined turn is detected, while when transmitting status information, Violation operations are enabled only within a certain period of time after the rise and fall of the status signal of each channel, and on the receiving side, the signal assigned to each channel is When two consecutive violations are detected at the same time and a predetermined pattern is detected, a coincidence pulse is generated, and when a preset number of coincidence pulses are detected within a predetermined time, the receiving side This is to control the status on or off, and will be explained in detail below using an example.

[Embodiments of the invention]

FIG. 1(,) and FIG. 1(b) are block diagrams showing an embodiment of the status information transmission method and device according to the present invention, and in particular, FIG. 1(,) shows the transmitting section thereof. , FIG. 1(b) shows the receiving section. In the same figure,
1 is the code sequence (bm) (just L, 4i at time nT
ibn is a value determined from bn=an■bn-2, where ■represents addition of modulo N); 2 is a 2-time slot (2T) delay circuit;
3 is a subtraction circuit that encodes to class IV P-R, 4 is a 4
(time slot) (4T) delay circuit, 5 is a polarity inversion circuit, 6 is an input code sequence (dml (time nTO value is d
1.8 and 9 are input channel A status signal R8-A and channel B status signal R8, respectively. -B, triggered at each rising change point of the status signal R8-C of channel C,
A monostaple multivibrator that generates a constant pulse of 1 MI [10.11 and 12 are the input channel A status signals R8-A, respectively.

A monostaple multivibrator that is triggered at each falling change point of the channel B status signal R8-B and the channel C status signal R8-C and generates a pulse with a constant time width; 13. 14 and 15 are the modulo N additions described above. The code sequence (bm) output from circuit 1 is input, and A pattern detection outputs a pulse when the A pattern, B pattern, and C pattern shown in Table 1 are detected in the code sequence (bml). 16 to 22 are the signals of the valley pattern detection results, the signals of the rising and falling detection results of the status (R8) @ of each channel, and the timing of the timing signals φ□ to φC. 23 is an OR circuit for calculating the logical sum of the output signals of the AND circuits 16 to 22 and outputting a polarity inversion signal vn to the polarity inversion circuit 5; 24 is an OR circuit for detecting the coincidence of the received signal r; (t)
A receiver 25 performs synchronous detection and reproduces and outputs the code sequence (dm□) to which the 7-ioration operation has been applied. A received signal bell detection circuit 26 monitors whether or not the signal is being received, and inputs a code sequence (dml) to which a violation operation has been applied, and detects a code sequence for which a violation operation has been performed on the transmitting side. Two consecutive violations of the coding rule are detected, and code errors caused by noise or the like in the transmission path are detected as discrete violations, as shown in Figure 4(a).
As shown in , two consecutive violation detection circuits 27, 28 and 29 output two consecutive violation codes of the class W P-R code rule, respectively, when the code sequence (dm□) given the violation operation is The code sequence (dm) pattern corresponding to the A pattern in Table 2, the code sequence 1dm) pattern corresponding to the B pattern in Table 20, and the code sequence (dm) corresponding to the C pattern in Table 2 are input.
), and outputs pattern detection signals x, y, and 2 shown in FIGS. 4(e) to 4(g), a pattern detection circuit 308- is output from this pattern detection circuit 27. The input of the output pulse serves as a reference signal for block synchronization of the receiver, and the input of two consecutive violation signals detected by the two consecutive violation detection circuit 26 generates the timing signal φ shown in FIG. 4(b). 0. Figure 4(c)
A block synchronization detection circuit 31 generates a timing signal φ8 shown in FIG. 4 and a timing signal φC shown in FIG. 4(d).
-36 are AND circuits, 37-42 are counters, 43 is a timer that synchronously resets the counters 31-42;
44 to 46 are flip-flop circuits, and 47 to 49 are AND circuits.

L discrimination timetable 1 Table 2 Note that (aml is a code string obtained by time-division multiplexing of each transmission data of multiple channels. In particular, Figure 2 (,) shows the conversion of 3-channel data into a 2-bit parallel code string. In the example above, 2
There are four possible states depending on the combination of bits. Further, symbols A, B, and C represent data of channels A, B, and C, respectively. However, assuming that the code has significant information for each time width T, the value at time nT is assumed to be an. T
□ is an input terminal to which this time-division multiplexed code string (ILm) is input. T and ~T are the timings at which the timing signal φ□ shown in FIG. 2(b), the timing signal φ8 shown in FIG. 2(c), and the timing signal φC shown in FIG. 2(d) are input, respectively. This is a signal input terminal, and this timing signal φ6. φ8 and φC are timing signals for allocating the time at which the violation control signal Vn is generated according to the status signals of channels A, B, and C, respectively. In particular, the timing signal φ□ is a code sequence (am
In order to provide a phase reference for block synchronization on the receiving side, it is used as a timing signal indicating the time to perform a violation operation of block synchronization. Therefore, if a violation is given when pattern A shown in Table 2 is detected at the pulse generation time of the timing signal φ, it is possible to provide a reference for achieving block synchronization in the receiving section. Also, T5. T6 and T are status signal input terminals to which a channel A status signal R8-A, a channel B status signal R8-B, and a channel C status signal R8-C are input, respectively. Further, Table 1 shows examples of patterns for channels A, B, and C when an is a four-valued signal of 0.1 and 2.3. Each of the values () to 3 in Table 1 is a value for each time 2T, and since values at adjacent times are not subject to pattern detection, it only indicates that a sign exists.
It is represented by an x mark. However, the above explanation is for explaining the operation at time nT, and is for explaining the operation at the next time (n
+1) At T, pattern detection is performed for the values in the portion marked with X. Further, the A pattern is used for transferring block synchronization information, and when detected coincident with the timing of the timing signal φ, a polarity inversion signal is generated. Block synchronization information needs to be resynchronized quickly when the receiving section loses synchronization due to a momentary interruption of the transmission path, so it is necessary to continue sending it while the data signal is being transmitted. Therefore, we set the conditions for block synchronization information transfer even for two types of pattern deviations, and set the frequency of occurrence of signals whose polarity can be reversed to be equal on average for positive values and negative values.
DC component 12 of code sequence (DM) after violation operation - Deterioration of the suppression effect is reduced. On the other hand, the B pattern is used to transfer the status information of each channel, and within a certain period of time after the rise of the status (R8) signal of each channel, the timing signal φ-φ is transmitted. A polarity inversion signal is generated when the detection coincides with the timing of . In addition, the C pattern is used to send information to stop the status information transfer of each channel, and within a certain period of time after the fall of the status (R8) signal of each channel, the timing signal φ□ to φC is When a match is detected, a polarity inversion signal is generated. Further, Table 2 shows the relationship between each pattern and the code sequence with inverted polarity. This table 2
The value Y on the code sequence (dm) in is of class W P-R
The value determined by the encoding rule, -2 or 2 with an O symbol, is the value determined according to the original encoding rule with the polarity reversed. In other words, the code marked with a circle is a code to which a violation was intentionally given on the transmitting side. Also, FIG. 3(a).

FIG. 3(b) and FIG. 3(C) are channel A, respectively.
status (No. i R8-A, !: output signal α of mono staple multi-via 'l/-37
#v is a diagram showing the relationship between the output signal β of the multivibrator 1o. In addition, Fig. 4(,) shows two consecutive violations, Fig. 4(b) to Fig. 4(d) show timing pulse φ correction to φC correction, and Fig. 4(e) to Fig. 4(g), respectively. )
C) This shows the timing of each turn detection, but 2
Individual consecutive violations and each pattern are detected only when a violation operation is performed in the transmitter.

Of course, it may also be detected due to a failure in the transmission path, but for such a failure, the method shown in Figure 1 (b)
It can be protected by providing collars 7fi37 to 42 of the receiving section shown in FIG.

Next, regarding the status information transmission method and the operation of the device with the above configuration, FIGS. 2(,) to 2(d),
This will be explained with reference to FIGS. 3(a) to 3(c) and FIGS. 4(8L) to 4(g). First, in the transmitting section shown in FIG.
, ) and the code sequence (&m) shown in 2 time slots (2T
) and the delayed signal output from the delay circuit 2. Then, the subtraction circuit 3 performs class y PR encoding by subtracting (bn-bn-s). and,
This encoded class PI PR code passes through a 4 time slot (4T) delay circuit 4, and then a code sequence (dm) in which a violation operation is added to the class IVP-R code by a polarity inversion circuit 5. is converted to Then, this code system old DML is sent to SSB-
It is sent out to the transmission path as AM signal transmission No. 4 5(t). Here, a violation operation for sending status information is performed only for a certain period of time after the rise and fall of the status signal of each channel, and the violation operation is prohibited at other times. An operation for minimizing interference with the DC component suppression effect on the code sequence will be described. First, status signal input terminal T
6. Channel A status signal R8-A and channel B status signal R8-A are applied to T and T7, respectively.
B and channel C status signals R8-C are input. Therefore, monostaple multivibrator 7
．． 8 and 9 are the respective status signals R8-A, R8-B and R
It is triggered at the rising change point of 8-C and outputs a pulse signal with a constant time width. Similarly, the monostable multivibrators 10, 11 and 12 are triggered at the falling change points of the status signals R8-A, R8-B and R8-C, respectively, and output pulse signals with a constant time width.

On the other hand, A pattern detection circuit 13° B pattern detection circuit 1
4 and C pattern detection circuit 15 receives the input of the code sequence (bm), and detects the code sequence (A on bml).
pattern, B pattern, and C pattern, and outputs a pulse. Here, the A pattern is used for block synchronization information transfer. Therefore, AND circuit 1
6 operates based on the logical product of the output signal of this human pattern detection circuit 13 and the timing signal φ□, and outputs an output signal. Therefore, the OR circuit 23 operates in response to the input of the output signal of the AND circuit 16, and outputs the polarity inversion signal vn. This block synchronization information must be resynchronized immediately if the receiving unit loses synchronization due to a momentary interruption of the transmission path, etc. Therefore, it is necessary to continue sending the block synchronization information while the data signal is being transmitted. There is. Therefore, we set the conditions for block synchronization information transfer for both of the two patterns, and set the frequency of occurrence of the signal whose polarity is inverted to be equal on average for positive values and negative values, so that the sign of the violation operation ffl is This reduces the deterioration of the direct current component suppression effect of the series (dm). The B pattern is then used to transfer status information for each channel. Therefore, the AND circuit 1T performs the logical product of the output signal of the B pattern detection circuit 14, the timing signal φ□ shown in FIG. 2(b), and the output signal α of the monostable multivibrator 17 shown in FIG. 3(b). , an output signal is output within a certain period of time after the status signal R8-A of channel A rises. Therefore, the OR circuit 23 operates in response to the input of the output signal of the AND circuit 17, and outputs the polarity inversion signal vn.

Similarly, the AND circuit 18 generates a channel B status signal R8-B by ANDing the output signal of the B pattern detection circuit 14, the timing signal φB shown in FIG. 2(c), and the output signal of the monostable multivibrator 8. The output signal is output within a certain period of time after the rise of . Therefore, the OR circuit 23 operates in response to the input of the output signal of the AND circuit 18, and outputs the polarity inversion signal vn. Similarly, the AND circuit 19 outputs the output signal of the B pattern detection circuit 14 and the second
The timing signal φ shown in FIG. and the output signal of the monostable multivibrator 9, an output signal is output within a certain period of time after the status signal R8-C of channel C rises. Next, the C pattern is used to send information for stopping the status information transfer of each channel. Therefore, the AND circuit 20 calculates the channel by ANDing the output signal of the C pattern detection circuit 15, the timing pulse shown in FIG. 2 (color), and the output signal β of the monostable multivibrator 10 shown in FIG. The output signal is output within a certain period of time after the fall of the status signal R8-A of A. Therefore, the OR circuit 23 operates in response to the input of the output signal of the AND circuit 20, and outputs the polarity inversion signal vn. Similarly, the AND circuit 21
Output signal of pattern detection circuit 15 and timing signal φ8
and the output signal of the monostable multivibrator 11, the channel B status signal R8-H
The output signal is output within a certain period of time after the falling edge of the signal. 1~ Therefore, the OR circuit 23 operates in response to the input of the output signal of the AND circuit 21, and outputs the polarity inversion signal vn.

Similarly, the AND circuit 22 receives the output signal of the C pattern detection circuit 15 and the timing signal φ. An output signal is output within a certain period of time after the fall of the status signal R8-C of channel C by the AND of the output signal of the monostable multivibrator 12. Therefore, the OR circuit 23 operates in response to the input of the output signal of the AND circuit 22, and outputs the polarity inversion signal vn. In this way, the relationship between each pattern shown in Table 1 and the polarity-inverted code sequence can be shown in Table 2. Therefore, if the A pattern shown in Table 2 is detected at the pulse generation time of the timing signal φA, a violation can be given to provide a reference for achieving block synchronization in the receiving section. In other words, if a pattern B matching the timing pulse φ is detected within a certain time width τ after the rise of the channel data signal R8-A, the violation operation shown in Table 2 is performed. It will be done. Also, the channel A status signal R8-
If the C pattern is detected by -fjt to the timing pulse φ□ within a certain time width τ□ after the fall of A, Table 2
The violation operation shown in is performed. therefore,
Violation operations for status signal transmission are prohibited except at certain times after the status signal rises and falls. Similarly, regarding the transmission of the status signal R8-H of channel B, the same violation operation as in the case of channel A is performed, except that it is made to match the timing signal φ8 shown in FIG. 2(c). Similarly, for channel C, the timing signal φ shown in FIG. 2(d) is used. Of course, the process is the same as channel A except that .

Next, in the transmitting section shown in FIG.
Code sequence violation operation was performed and 88B
20- The converted transmission No. 4 5(t) is received via the transmission line as the reception No. 4 r(1) by the receiving section shown in FIG. 1(b). Therefore, the received No. 4 r(1) is synchronously detected by the receiver 24, and the code sequence (dm, l) is reproduced.

Of course, if there is no code error during transmission, the code sequence (d
m)-(dml)Totoru. On the other hand, the received signal detection circuit 2
5 monitors the level of the receiving number 4 r(1), and monitors whether it is being received at a normal level. and,
Given code sequence of violation operation (dml)
is added to the class IV P-R code rule violation detection circuit 26, and code rule violations are detected twice consecutively for the code in which a violation operation has been performed on the transmitting side, and transmission due to noise etc. Code errors caused by traffic are detected as discrete violations.

Further, the code sequence (ami) is simultaneously input to pattern detection circuits 27, 28 and 29. Therefore, the pattern detection circuit 27 detects the code sequence (dm) pattern corresponding to the A pattern shown in Table 2, and the pattern detection circuit 28 detects the code sequence fdm corresponding to the B pattern shown in Table 2.
), and the pattern detection circuit 29 detects a code sequence (dm) pattern corresponding to the C pattern shown in Table 2. Therefore, first, when the pattern detection circuit 2T supplies the detection signal X shown in FIG. 4(e) to the block synchronization detection circuit 30, this detection signal Input as a signal. Therefore, when the two consecutive violation pulses detected by the pattern detection circuit 26 are input to the block synchronization detection circuit 30 and this detection signal
Timing pulses φAllφ8□ and φC shown in d)
Output the process. Next, for example, the reception operation of the status signal R8-A of channel A will be explained.
), a timing pulse φ is generated within a certain period of time after the rise of the channel A status signal R8-A.
If there is no code error on the transmission path, the B pattern of the code sequence (dm) in Table 2, which is given a violation in synchronization with , is reproduced by the receiver 26 as the code sequence (dm)=(dmx). Therefore, when the code sequence (dml B pattern) is reproduced, the violation detection circuit 26
Pattern detection circuit 2 detects individual consecutive violations.
8 detects the B pattern. If these detection times coincide with the timing pulse φA1 shown in FIG. Therefore, counter 3
7 is periodically reset by a timer 43 at certain time intervals, but if it counts 7 coincidence detection pulses before being reset, it outputs a count pulse to the flip-flop 44. For this reason, the flip-flop 44
is set. If the received signal r(t) is at the correct level and is not received, the received signal is sent to the bell detection circuit 25.
outputs a high level signal to AND gates 47-49. Therefore, since flip-flop 44 of AND gate 47 is set, its output signal CD-A rises from low level to high level, and status signal R8-A of channel A is detected. On the other hand, Figure 1 (,)
When the status signal R8-A of channel A is set to low level (status signal R8-A is turned off) in the transmitting unit shown in 23-, the second Timing pulse φ shown in figure (b). In synchronization with , the C pattern of the code sequence (dm) in Table 2 to which a violation has been given is transmitted, and if there is no code error, the C pattern is reproduced by the receiving section shown in FIG. 1(b). Then, when the C pattern is reproduced, the violation detection circuit 26 detects two consecutive violations, and the pattern detection circuit 29 detects the C pattern.

If these detection times and the timing pulse φ4 match, it is detected by the AND gate 34, and a match detection pulse is output to the counter 40.

Therefore, the counter 40 is reset 11 synchronously by the timer 43, and when zero coincidence detection pulses are counted within a certain fixed period of time, a count pulse is output. Therefore, the flip-flop 44 is reset by inputting this count pulse. therefore,
The output signal CD-A of the AND gate 4724- changes from high level to low level, and it is possible to detect the status of channel A (OFF of IR8-A) on the transmitting side.

Note that the code sequence (dnn) is the code sequence (,) shown in Figure 1 (,).
It is also supplied to the decoding circuit for playing DM4,
Of course, a known method can be used for the decoding method. Furthermore, as for block synchronization, it goes without saying that protection against out-of-synchronization is required. In addition, although the above has been explained for the case of channel A,
Of course, in the case of channel B, it operates in the same manner as in the case of channel A, except that it operates in synchronization with the timing signal φBl and in the case of channel C, the timing signal φc0.

〔Effect of the invention〕

As explained in detail above, according to the status information transmission method and device according to the present invention, when transmitting multi-channel status signals, only a certain period of time between the rise and fall of the status signal of each channel is transmitted. Since the deterioration of the original data transmission caused by the violation operation can be minimized, the data transmission system can be operated smoothly.

[Brief explanation of the drawing]

FIG. 1(a) and FIG. 1Φ) are block diagrams showing an embodiment of the status information transmission method and device according to the present invention, FIGS. 2(a) to 2(d), and FIG. (a
) to FIG. 3(c) are diagrams showing the waveforms of each part of the transmitting section shown in FIG. 1(a), and FIG.
It is a figure which shows the waveform of each part of the receiving part shown in b). 1... Modulo N addition circuit, 2... 2 time slot (2T) delay circuit, 3... Subtraction circuit, 4...
... 4 time slot delay circuit, 5 ... polarity reversal circuit, 6 ... transmitter, 7-9 ... monostaple multivibrator triggered at rising point, 10-1
2... Mono staple multivibrator triggered at falling point, 13... A pattern detector, 14
...B pattern detector, 15...C pattern detector, 16-22...AND circuit, 23...OR circuit, 24...receiver, 25... Received signal level detection circuit, 26...2 continuous violation detection circuit, 27-29...pattern detection circuit, 30
...Block synchronization detection circuit, 31=36...And gate, 37-42...Counter, 43...
・Timer, 44-46...7 lip-flop circuit,
4T~49...and gate. Patent applicant: Masaki Yamakawa, agent for NEC Corporation (12 people)

Claims (1)

[Claims] (Class 11) In a status information transmission method in which status information is transmitted by intentionally giving a violation to a partial response coded code sequence, for synchronizing blocks on the transmitting side. When transmitting information, polarity reversal control is performed continuously under the condition that a violation operation is performed only when a predetermined pattern is detected, while when transmitting status information, the status signal of each channel is Violation operations are enabled only within a certain period of time after rising and falling, and on the receiving side, two signals are sent at the time assigned to each channel under the condition that the received signal and bell are at the normal level. When continuous violations are detected and a predetermined pattern is detected, a match pulse is generated, and when a preset number of match pulses are detected within a predetermined time, the receiving side status is turned on or off. A status information transmission method characterized by: (2) Class ■In a status information transmission device that transmits status information by intentionally giving a violation to a partial response encoded code sequence, the status signal of each channel is A mono-staple multivibrator that generates a pulse with a fixed time width after the rise and fall of a plurality of AND circuits that match the circuit with a timing signal that limits the time when a violation is given according to the output of the monostaple multivibrator, the output of the pattern detection circuit, and the status signal of each channel; A transmitting section consisting of an OR circuit that takes the logical sum of the outputs of the plurality of AND circuits, and a circuit that inverts the polarity of the class ■ partial response encoded code using the output signal of the OR circuit; a signal detection circuit for monitoring the level of code 4, a circuit for detecting two consecutive violations from a reproduced code sequence to which a violation operation has been added, and a circuit for detecting different patterns in the code sequence. a plurality of pattern detection circuits;
A circuit that synchronizes blocks from the output signal of a pattern detection circuit assigned for individual consecutive violations and block synchronization, and a timing signal that allocates time for each channel generated from this circuit that synchronizes blocks. a plurality of AND circuits that match the timing signal of the output of the pattern detection circuit with a timing signal of the output of the pattern detection circuit, a plurality of counter circuits that count the output pulses of each AND circuit, and a reset pulse is supplied to the counter circuit at a constant cycle. a timer circuit, a plurality of flip-flop circuits controlled by the output of the counter circuit, and a plurality of AND circuits that perform a logical product of the output of the flip-flop circuit and the output of the received signal/bell detection circuit. What is claimed is: 1. A status information transmitting device comprising: a receiving section configured as shown in FIG.