JPS59172871A - Channel synchronism circuit applied to multichannel separating device for receiving - Google Patents

Abstract

PURPOSE:To stabilize the channel synchronism by executing phase control only when two consecutive violations are detected in the form of a specific pattern among N sets of received symbols. CONSTITUTION:In order to prevent an erroneous phase control from being executed when a channel synchronism circuit 9 is synchronized correctly, the phase control is executed by detecting two consecutive violations in the form of specific pattern among N sets of received symbols. That is, when a signal (u) is not obtained in a counter 21, a flip-flop 23 is not set and no phase change is given to each output signal of a frequency-division circuit 18. In case of the out of synchronism of channel, no pulse appears at an output of an AND circuit 12 and when a signal (t) reaches a low level, since a clock signal (m) cannot passes through an AND circuit 10, the phase of each output signal of the frequency division circuit 18 is parted for one period's share of the clock signal (m) during that time and the channel synchronism is established.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel synchronization circuit on the receiving side in a time division multiplex transmission system for multi-channel channel signals by encoding.

Multi-channel signals are time-division multiplexed and transmitted.

In order to separate this in the receiving section, it is generally necessary to send a signal for out-of-channel synchronization from the transmitting section. However, when applying class ■ general response encoding to a multi-channel signal, the transmitting section transmits a violation that disturbs the encoding rule under certain conditions. The violation characteristically detected by the receiver is used as a phase reference signal.

This allows efficient data transmission without allocating time for sending channel synchronization signals. This is described in detail in the specification of Japanese Patent Application No. 57-26,823, so please refer to it. As a condition for giving the above violation.

In order to provide a phase reference for channel synchronization, the code of a particular channel must be given to the existing time position (time slot), and in order to obtain a characteristic violation in the receiver, it must be determined in the transmitter. It is necessary to provide this when a specific combination of codes can be derived from the precoated code sequence. However, as a result, the channel synchronization signal depends on the pattern of the transmitted code sequence, the degree of occurrence is stochastic, there is no temporal regularity, and the signal is interfered with on the transmission path. There was a drawback that synchronization was disrupted.

An object of the present invention is to perform phase control only when two consecutive violations due to specific/F turns are detected in N received symbols.

An object of the present invention is to provide a channel synchronization circuit capable of achieving stable channel synchronization even when a channel synchronization signal is generated irregularly in time and is disturbed on a transmission path.

According to the present invention, the class ■ and -character response encoding is performed with a specific code lean of the code sequence.

It is also applied to a multi-channel demultiplexing device for reception in a time division multiplex transmission system that transmits by giving a time slot of a specific channel, and outputs a signal after counting N received non-poles. 1 count output circuit, a circuit that generates a signal when the specific code lean is detected on the received code sequence and two consecutive pie rays/yons are detected at the same time, and a circuit synchronized with the received code. A circuit for dividing the frequency of a clock signal, a circuit for taking an AND of the frequency-divided signal and the output pulse of the signal generating circuit, and the first count output circuit count N received symbols. a second output circuit that outputs a signal when two consecutive violations have been detected before; When Gurus crabs are counted,
a third count output circuit that outputs a Q pulse;
and a circuit that generates a phase control pulse in response to the third count output, and detects a specific Q-coon on the received code sequence while receiving N symbols, and detects two consecutive violations. A channel synchronization circuit, characterized in that, when the number of pulses obtained when detected is greater than or equal to the number of pulses, the driving power of the frequency dividing circuit is controlled by the output pulse of the phase control pulse generation circuit. is obtained.

Next, a synchronous circuit according to the present invention will be described in detail with reference to the drawings.

FIGS. 1 and 2 respectively show a block diagram of a receiving section and a quill yard as an embodiment of the present invention. In FIG. 1, a received signal a supplied via a transmission path is demodulated by a demodulation circuit 1, equalized and dinkled at the same time by an automatic equalizer 2, and the two-hit code and polarity of this signal are It is converted into a parallel signal (signal b in FIG. 2) consisting of a total of three pinots □ of sign hints indicating .

Further, the presence or absence of the received signal a is determined by the signal detection circuit 3, and the result is output as a determination signal g.

The parallel signals mentioned above are simultaneously applied to the violation detection circuit 4, the parallel-to-serial code conversion circuit 6, and the channel synchronization circuit 9 of the class Ⅰ partial response encoding rule. Of these, the violation detection circuit 4 compares the signal with the encoding rule to detect a violation of the encoding rule, that is, a violation. Further, a violation intentionally added to indicate a phase reference for channel synchronization in the transmitting section is detected as two consecutive violations, and the information thereof is output as a signal e. Note 7
When two consecutive violations are detected, the signal C is not considered as a code error in the received signal, but when a single violation is detected, the signal C is output as code error information. This signal C is applied to the error car detection circuit 5, which detects the error rate, and converts the parallel code sequence shown in FIG. 2 into a serial code sequence f based on the signal provided.

If this signal f is scrambled in the transmitter, it is decoded in the scramble circuit 7 and then serially transmitted.
+J as shown in FIG.
It is converted into + and 1 signs. The cell synchronization circuit 9 is a circuit according to the present invention, in which the demodulation circuit 1 is time-division multiplexed, and the demodulation circuit 1 is time-division multiplexed. When receiving a signal with a violation only in ~, restoring it to the output signal, and performing further channel separation, this dial synchronization circuit 9 converts the code conversion signal and i. Occur.

FIG. 3 is a block diagram showing an example of the configuration of the channel synchronization circuit 9 in FIG. 1.

In this figure, 10, 11, 12, and 13 are AND circuits, 14 is an OR circuit, and 15 is a NAND AND circuit.

17 is an impark circuit, 18 is a fi frequency dividing circuit, 19 is an N-stage counter, 20 is an /F turn detection circuit, 21°22 is a second-stage counter, and 23, 24, 2! 5 are flip-flop circuits. Further, 2m is a clock signal synchronized with the signal s in FIG. 2, and n is a baud clock signal obtained by dividing the signal m. The operation of the channel synchronization circuit configured as described above will be described below with reference to Quimchar I. of FIG.

In FIG. 3, the N stage counter 9 generates a positive signal 〇 every time it counts N baud clock signals n, and the stage counters 21 and 22 and the flip-flop circuit 23
．． 24, respectively. The pattern detection circuit 2o generates a signal when it detects a predetermined pattern from the signal sequence. At the time of detecting this turn, two continuous pile-on detection signals e are simultaneously supplied from the pile-on detection circuits 4A and 4.

As shown in FIG. 2, a signal U is obtained at the output of the AND circuit 11. The frequency dividing circuit 18 divides the frequency of the clock signal m passing through the AND circuit 10 and generates each hllTV signal. The K-stage counter 21 is given the ξ pulse signal U.
A pulse p is generated every time the number of pulses is counted.

On the other hand 1. The second stage counter 22 receives the signal U through the AND circuit 12 only when the phase relationship between the signals U and V is as shown in FIG. , every time you count the above-mentioned gurus, the 4th
Generate pulse q in the figure. 797707021 circuit 2
3 is set by the signal p and reset by the signal 0 to generate the signal r. 797707021 circuit 24 receives signal q
, or is set by the output signal of the AND circuit 13,
It is reset by signal 7 and generates signal S. The flip-flop circuit 25 is a circuit that sets the output state of the NAND circuit 15 at the rising edge of the clock signal m, thereby outputting the signal t. Note that the states of the signals g and d applied to the AND circuit 15 are 2 under normal transmission conditions.
In other words, there is no disconnection in the transmission path, and signal a is correctly received.
If the error rate also satisfies the specified conditions, it is assumed that it is logically set to a high level.

Here, a case where the channel synchronization circuit 9 is properly synchronized and a case where the channel synchronization circuit 9 is out of synchronization will be explained.

First, when channel synchronization is achieved, the phase relationship between signals U and V is as shown by the solid line in FIG. Therefore, the operating state of each circuit in the channel synchronization circuit 9 is as shown by the solid line in FIG. The problem here is the old signal U.
Considering the frequency of occurrence of pulses, the conditions for the generation of pulses are such that a specific green is detected in the code sequence transmitted by the transmitter, and a violation is given only in the code assignment check slot of a specific channel.

The receiver detects a specific pattern in the received code sequence.

It can be seen that this occurs only when two consecutive violations are detected. Therefore, the way in which the ``Gurus'' is generated is stochastic, and there is a state in which the ``Gurus'' of the signal U does not occur for a long period of time. In order to prevent erroneous phase control from being performed in such cases, phase control is performed by detecting two consecutive violations due to specific/lean signals in the received symbols of the N fixed signal. . That is, when the counter circuit 21 cannot obtain the signal U.

Since the positive signal p is not generated on the output side, the flip-flop circuit 23 is not set. Therefore, the signal t
is at a high level and does not give any phase change to each output signal of the divide-by-9 frequency circuit 18.

In the case of channel synchronization, the phase relationship between signals U and V becomes 7.For example, as shown by the broken line in Fig. 2, AN
No glucose appears in the output of the D circuit 12. Therefore, the signals q, S, and t have a relationship as shown by the broken line in the time chart. In this way, when the signal t is at a low level, the clock signal m does not pass through the AND circuit 10.

During this time, the phase of each output signal of the divide-by-2 circuit 18 is delayed by one period of the clock signal m. Note that the AND circuit 13 is used to set the inhibition time of the clock signal m by the signal t to one period of the clock signal m per NT seconds. However, 2 hours T is the time of one period of peak lock. The above-mentioned state of out-of-synchronization continues until the generation position of the signal (2) reaches the position indicated by the solid line in FIG. 2, after which channel synchronization is established.

In the above embodiment, only the operation in the normal transmission state was explained, but as a synchronization protection method in the event of a disturbance in the transmission path or a line disconnection, the signal g When the error rate of the received code exceeds the specified value due to random occurrence, the signal d is set to a low level and the signal t is set to a high level unconditionally to prevent any errors. Therefore, it is possible to prevent phase control from being performed.

As is clear from the above explanation, according to the present invention, N
By performing phase control only when two consecutive violations are detected in the received symbols, the channel can be stably maintained even for channel synchronization signals that are received irregularly over a two-hour period. The advantages are significant in that synchronization can be established and system reliability can be maintained even in the face of signal interference on the transmission path.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a receiving section as an embodiment of the present invention, and FIG. 2 is a diagram for explaining the operation of the embodiment in FIG. FIG. 3 is a block diagram showing a configuration example of the channel synchronization circuit in FIG. 1, and FIG. 4 is a time chart 1 for explaining the operation of the channel synchronization circuit in FIG. In the figure, ] is a demodulation circuit, and 2 is an automatic equalizer. 3 is a signal detection circuit, 4 is a violation detection circuit, 5
is an error vehicle detection circuit, 6 is a parallel-to-serial code conversion circuit, 7 is a screen scramble circuit, 8 is a series-to-parallel code conversion circuit,
9 is a channel synchronization circuit, 10 to 13 are AND circuits, 14
is an OR circuit, 15 is a NAND AND circuit, 6, 17
18 is an impark circuit, 18 is a frequency dividing circuit, 19 is an N-stage counter, 20 is a main turn detection circuit, 21.22 is a second-stage counter, and 23-25 are flip-flop circuits.

Claims (1)

[Claims] 1 Class N/'? - Applied to a multi-channel demultiplexing device for reception in a time division multiplex transmission system that transmits a specific code pattern of a social response code coded group code sequence and with violations in the time slot of a specific channel, a first count output circuit that outputs a pulse each time a pulse is counted; and a first count output circuit that generates a pulse when the specific code pattern is detected on the received code sequence and two consecutive violations are detected at the same time. a circuit for frequency-dividing a clock signal synchronized with a received code; a circuit for ANDing the frequency-divided signal and the output pulse of the pulse generation circuit;
- a second count output circuit that outputs a pulse if two consecutive violations are detected before the output circuit has counted N received symbols, and also before the output circuit has counted N received symbols; a third count output circuit that outputs a pulse when the output pulses of the AND circuit are counted; and a third count output circuit that receives the second and third count outputs and generates a phase control pulse. Equipped with a circuit. If a specific ``coon'' is detected on the received code sequence while receiving N symbols, and the number of ``coons'' obtained when two consecutive violations are detected, A channel synchronization circuit characterized in that one drive input of the frequency dividing circuit is controlled by an output signal of the phase control pulse generation circuit.